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参数资料
| 型号： | M95256-RDW3/A |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 32K X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封装： | 0.169 INCH, TSSOP-8 |
| 文件页数： | 7/43页 |
| 文件大小： | 431K |
| 代理商： | M95256-RDW3/A |
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M95256, M95256-W, M95256-R
Instructions
15/42
5.3
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Write or Write Status Register cycle
is in progress. When one of these cycles is in progress, it is recommended to check the
Write In Progress (WIP) bit before sending a new instruction to the device. It is also possible
to read the Status Register continuously, as shown in Figure 7.
The status and control bits of the Status Register are as follows:
5.3.1
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write or Write
Status Register cycle. When set to 1, such a cycle is in progress, when reset to 0 no such
cycle is in progress.
5.3.2
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write or Write Status Register instruction is accepted.
5.3.3
BP1, BP0 bits
The Block Protect (BP1, BP0) bits are non-volatile. They define the size of the area to be
software protected against Write instructions. These bits are written with the Write Status
Register (WRSR) instruction. When one or both of the Block Protect (BP1, BP0) bits is set to
1, the relevant memory area (as defined in Table 4) becomes protected against Write
(WRITE) instructions. The Block Protect (BP1, BP0) bits can be written provided that the
Hardware Protected mode has not been set.
5.3.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP1, BP0) become read-only bits and the
Write Status Register (WRSR) instruction is no longer accepted for execution.
Table 4.
Status Register Format
b7
b0
SRWD
0
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect Bits
Write Enable Latch Bit
Write In Progress Bit
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M95256RDW3G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit serial SPI bus EEPROM with high-speed clock |
| M95256-RDW3G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256Kbit and 128Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95256-RDW3G/A | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit Serial SPI bus EEPROM with high speed clock |
| M95256-RDW3G/K | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit serial SPI bus EEPROM with high-speed clock |
| M95256-RDW3G/V | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit Serial SPI bus EEPROM with high speed clock |
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