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参数资料
| 型号： | M95256-RDW3/A |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 32K X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封装： | 0.169 INCH, TSSOP-8 |
| 文件页数： | 16/43页 |
| 文件大小： | 431K |
| 代理商： | M95256-RDW3/A |
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M95256, M95256-W, M95256-R
Delivery state
23/42
6
Delivery state
The device is delivered with the memory array set at all 1s (FFh). The Status Register Write
Disable (SRWD) and Block Protect (BP1 and BP0) bits are initialized to 0.
7
Connecting to the SPI bus
These devices are fully compatible with the SPI protocol.
All instructions, addresses and input data bytes are shifted in to the device, most significant
bit first. The Serial Data Input (D) is sampled on the first rising edge of the Serial Clock (C)
after Chip Select (S) goes Low.
All output data bytes are shifted out of the device, most significant bit first. The Serial Data
Output (Q) is latched on the first falling edge of the Serial Clock (C) after the instruction
(such as the Read from Memory Array and Read Status Register instructions) have been
clocked into the device.
Figure 12 shows three devices, connected to an MCU, on a SPI bus. Only one device is
selected at a time, so only one device drives the Serial Data Output (Q) line at a time, all the
others being high impedance.
Figure 12. Bus Master and Memory Devices on the SPI Bus
1.
The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
2.
These pull-up resistors, R, ensure that the M95256, M95256-W, M95256-R are not selected if the Bus Master leaves the S
line in the high-impedance state. As the Bus Master may enter a state where all inputs/outputs are in high impedance at the
same time (that is when the Bus Master is reset), the clock line (C) must be connected to an external pull-down resistor so
that, when all inputs/outputs become high impedance, S is pulled High while C is pulled Low (thus ensuring that S and C do
not become High at the same time, and so, that the tSHCH requirement is met).
AI12304
Bus Master
(ST6, ST7, ST9,
ST10, Others)
SPI Memory
Device
SDO
SDI
SCK
CQD
S
SPI Memory
Device
CQD
S
SPI Memory
Device
CQD
S
CS3
CS2
CS1
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
W
HOLD
W
HOLD
W
HOLD
R(2)
VCC
VSS
R(2)
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M95256RDW3G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit serial SPI bus EEPROM with high-speed clock |
| M95256-RDW3G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256Kbit and 128Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95256-RDW3G/A | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit Serial SPI bus EEPROM with high speed clock |
| M95256-RDW3G/K | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit serial SPI bus EEPROM with high-speed clock |
| M95256-RDW3G/V | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit Serial SPI bus EEPROM with high speed clock |
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