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参数资料
| 型号： | M95256-RDW3/A |
| 厂商： | STMICROELECTRONICS |
| 元件分类： | PROM |
| 英文描述： | 32K X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| 封装： | 0.169 INCH, TSSOP-8 |
| 文件页数： | 9/43页 |
| 文件大小： | 431K |
| 代理商： | M95256-RDW3/A |
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M95256, M95256-W, M95256-R
Instructions
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5.4
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data Input (D).
The instruction sequence is shown in Figure 8.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b4, b1 and b0 of the
Status Register. b6, b5 and b4 are always read as 0.
Chip Select (S) must be driven High after the rising edge of Serial Clock (C) that latches in
the eighth bit of the data byte, and before the next rising edge of Serial Clock (C). Otherwise,
the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select (S) is
driven High, the self-timed Write Status Register cycle (whose duration is tW) is initiated.
While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Write Status Register cycle, and is 0 when it is completed. When the
cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP1, BP0) bits, to define the size of the area that is to be treated as read-
only, as defined in Table 4.
The Write Status Register (WRSR) instruction also allows the user to set or reset the Status
Register Write Disable (SRWD) bit in accordance with the Write Protect (W) signal. The
Status Register Write Disable (SRWD) bit and Write Protect (W) signal allow the device to
be put in the Hardware Protected Mode (HPM). The Write Status Register (WRSR)
instruction is not executed once the Hardware Protected Mode (HPM) is entered.
The contents of the Status Register Write Disable (SRWD) and Block Protect (BP1, BP0)
bits are frozen at their current values from just before the start of the execution of Write
Status Register (WRSR) instruction. The new, updated, values take effect at the moment of
completion of the execution of Write Status Register (WRSR) instruction.
相关PDF资料 |
PDF描述 |
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| M95256-RMN6P/A | 32K X 8 SPI BUS SERIAL EEPROM, PDSO8 |
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| M95256-RDW6TG | 32K X 8 SPI BUS SERIAL EEPROM, PDSO8 |
| MA-306-29.4912M-K0 | QUARTZ CRYSTAL RESONATOR, 29.4912 MHz |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| M95256RDW3G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit serial SPI bus EEPROM with high-speed clock |
| M95256-RDW3G | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256Kbit and 128Kbit Serial SPI Bus EEPROM With High Speed Clock |
| M95256-RDW3G/A | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit Serial SPI bus EEPROM with high speed clock |
| M95256-RDW3G/K | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit serial SPI bus EEPROM with high-speed clock |
| M95256-RDW3G/V | 制造商:STMICROELECTRONICS 制造商全称:STMicroelectronics 功能描述:256 Kbit Serial SPI bus EEPROM with high speed clock |
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