参数资料
型号: MAX1038AEEE+T
厂商: Maxim Integrated Products
文件页数: 18/23页
文件大小: 0K
描述: IC ADC 8BIT LP SERIAL 16-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 8
采样率(每秒): 188k
数据接口: I²C,串行
转换器数目: 1
功率耗散(最大): 1.75mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 带卷 (TR)
输入数目和类型: 12 个单端,单极;12 个单端,双极;6 个伪差分,单极;6 个伪差分,双极
MAX1036–MAX1039
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel 2-Wire Serial 8-Bit ADCs
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX1037/MAX1039), VDD = 4.5V to 5.5V (MAX1036/MAX1038). External reference, VREF = 2.048V
(MAX1037/MAX1039), VREF = 4.096V (MAX1036/MAX1038). External clock, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
MAX1037/MAX1039
2.7
3.6
Supply Voltage (Note 10)
VDD
MAX1036/MAX1038
4.5
5.5
V
Internal REF, external clock
350
650
fSAMPLE =
188ksps
External REF, external clock
250
External REF, external clock
110
fSAMPLE =
75ksps
External REF, internal clock
150
External REF, external clock
8
fSAMPLE =
10ksps
External REF, internal clock
10
External REF, external clock
2
fSAMPLE =
1ksps
External REF, internal clock
2.5
Supply Current
IDD
Power-down
1
10
A
Power-Supply Rejection Ratio
PSRR
(Note 11)
±0.25
±1
LSB/V
TIMING CHARACTERISTICS FOR 2-WIRE FAST MODE (Figures 1A and 2)
Serial Clock Frequency
fSCL
400
kHz
Bus Free Time Between a STOP
and a START Condition
tBUF
1.3
s
Hold Time for Start Condition
tHD, STA
0.6
s
Low Period of the SCL Clock
tLOW
1.3
s
High Period of the SCL Clock
tHIGH
0.6
s
Setup Time for a Repeated START
Condition (Sr)
tSU, STA
0.6
s
Data Hold Time
tHD, DAT
(Note 12)
0
150
ns
Data Setup Time
tSU, DAT
100
ns
Rise Time of Both SDA and SCL
Signals, Receiving
tR
(Note 13)
20 + 0.1CB
300
ns
Fall Time of SDA Transmitting
tF
(Note 13)
20 + 0.1CB
300
ns
Setup Time for STOP Condition
tSU, STO
0.6
s
Capacitive Load for Each Bus Line
CB
400
pF
Pulse Width of Spike Suppressed
tSP
50
ns
TIMING CHARACTERISTICS FOR 2-WIRE HIGH-SPEED MODE (Figures 1B and 2)
Serial Clock Frequency
fSCLH
(Note 14)
1.7
MHz
Hold Time (Repeated) Start
Condition
tHD, STA
160
ns
Low Period of the SCL Clock
tLOW
320
ns
High Period of the SCL Clock
tHIGH
120
ns
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