参数资料
型号: MAX1038AEEE+T
厂商: Maxim Integrated Products
文件页数: 19/23页
文件大小: 0K
描述: IC ADC 8BIT LP SERIAL 16-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
位数: 8
采样率(每秒): 188k
数据接口: I²C,串行
转换器数目: 1
功率耗散(最大): 1.75mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SSOP(0.154",3.90mm 宽)
供应商设备封装: 16-QSOP
包装: 带卷 (TR)
输入数目和类型: 12 个单端,单极;12 个单端,双极;6 个伪差分,单极;6 个伪差分,双极
MAX1036–MAX1039
2.7V to 3.6V and 4.5V to 5.5V, Low-Power,
4-/12-Channel 2-Wire Serial 8-Bit ADCs
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 2.7V to 3.6V (MAX1037/MAX1039), VDD = 4.5V to 5.5V (MAX1036/MAX1038). External reference, VREF = 2.048V
(MAX1037/MAX1039), VREF = 4.096V (MAX1036/MAX1038). External clock, fSCL = 1.7MHz, TA = TMIN to TMAX, unless otherwise
noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Setup Time for a Repeated START
Condition (Sr)
tSU, STA
160
ns
Data Hold Time
tHD, DAT
(Note 12)
0
150
ns
Data Setup Time
tSU, DAT
10
ns
Rise Time of SCL Signal
(Current Source Enabled)
tRCL
(Note 13)
20
80
ns
Rise Time of SCL Signal After
Acknowledge Bit
tRCL1
(Note 13)
20
160
ns
Fall Time of SCL Signal
tFCL
(Note 13)
20
80
ns
Rise Time of SDA Signal
tRDA
(Note 13)
20
160
ns
Fall Time of SDA Signal
tFDA
(Note 13)
20
160
ns
Setup Time for STOP Condition
tSU, STO
160
ns
Capacitive Load for Each Bus Line
CB
400
pF
Pulse Width of Spike Suppressed
tSP
010
ns
Note 1: The MAX1036/MAX1038 are tested at VDD = 5V and the MAX1037/MAX1039 are tested at VDD = 3V. All devices are config-
ured for unipolar, single-ended inputs.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and
offsets have been calibrated.
Note 3: Offset nulled.
Note 4: Ground on channel; sine wave applied to all off channels.
Note 5: Conversion time is defined as the number of clock cycles (8) multiplied by the clock period. Conversion time does not
include acquisition time. SCL is the conversion clock in the external clock mode.
Note 6: The absolute voltage range for the analog inputs (AIN0–AIN11) is from GND to VDD.
Note 7: When AIN_/REF is configured to be an internal reference (SEL[2:1] = 11), decouple AIN_/REF to GND with a 0.01F capacitor.
Note 8: The switch connecting the reference buffer to AIN_/REF has a typical on-resistance of 675Ω.
Note 9: ADC performance is limited by the converter’s noise floor, typically 1.4mVP-P.
Note 10: Electrical characteristics are guaranteed from VDD(min) to VDD(max). For operation beyond this range, see the Typical
Operating Characteristics.
Note 11: Power-supply rejection ratio is measured as:
, for the MAX1037/MAX1039 where N is the number of bits and VREF = 2.048V.
Power-supply rejection ratio is measured as:
, for the MAX1036/MAX1038 where N is the number of bits and VREF = 4.096V.
Note 12: A master device must provide a data hold time for SDA (referred to VIL of SCL) in order to bridge the undefined region of
SCL’s falling edge (Figure 1).
Note 13: CB = total capacitance of one bus line in pF. tR, tFDA, and tF measured between 0.3VDD and 0.7VDD. The minimum value is
specified at +25°C with CB = 400pF.
Note 14: fSCLH must meet the minimum clock low time plus the rise/fall times.
VV
V
VV
FS
N
REF
55
45
2
55
45
..
() ()
[]×
VV
V
VV
FS
N
REF
33
27
2
33
27
..
() ()
[]×
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