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参数资料
| 型号： | MAX1124EGK+TD |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/17页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT PAR 250MSPS 68QFN |
| 标准包装： | 2,500 |
| 位数： | 10 |
| 采样率（每秒）： | 250M |
| 数据接口： | LVDS，并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 657mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | * |
| 封装/外壳： | * |
| 供应商设备封装： | * |
| 包装： | * |
| 输入数目和类型： | 1 个单端，单极；1 个差分，单极 |
Analog Inputs (INP, INN)
INP and INN are the fully differential inputs of the
MAX1124. Differential inputs usually feature good rejec-
tion of even-order harmonics, which allows for enhanced
AC performance as the signals are progressing through
the analog stages. The MAX1124 analog inputs are self-
biased at a common-mode voltage of 1.4V and allow a
differential input voltage swing of 1.25VP-P. Both inputs
are self-biased through 2.2kΩ resistors, resulting in a
typical differential input resistance of 4.4kΩ. It is recom-
mended to drive the analog inputs of the MAX1124 in
AC-coupled configuration to achieve best dynamic per-
formance. See the
AC-Coupled Analog Inputs section for
a detailed discussion of this configuration.
On-Chip Reference Circuit
The MAX1124 features an internal 1.23V bandgap ref-
erence circuit (Figure 3), which, in combination with an
internal reference-scaling amplifier, determines the full-
scale range of the MAX1124. Bypass REFIO with a
0.1F capacitor to AGND. To compensate for gain
errors or increase the ADC’s full-scale range, the volt-
age of this bandgap reference can be indirectly adjust-
ed by adding an external resistor (e.g., 100kΩ trim
potentiometer) between REFADJ and AGND or REFADJ
and REFIO. See the
Applications Information section for
a detailed description of this process.
Clock Inputs (CLKP, CLKN)
Designed for a differential LVDS clock input drive, it is
recommended to drive the clock inputs of the MAX1124
MAX1124
1.8V, 10-Bit, 250Msps Analog-to-Digital Converter
with LVDS Outputs for Wideband Applications
______________________________________________________________________________________
11
INP
INN
D0P/N–D9P/N
ORP/N
CLKP
CLKN
tCH
tCL
DCLKP
DCLKN
N - 8
N - 7
N
N + 1
tPDL
N - 7
N - 8
N
N + 1
N
N + 1
N + 8
N + 9
tCPDL
tLATENCY
tAD
N - 1
SAMPLING EVENT
tCPDL - tPDL
tCPDL - tPDL ~ 0.4 x tSAMPLE with tSAMPLE = 1/fSAMPLE
NOTE: THE ADC SAMPLES ON THE RISING EDGE OF CLKP. THE RISING EDGE OF DCLKP CAN BE USED TO EXTERNALLY LATCH THE OUTPUT DATA.
Figure 4. System and Output Timing Diagram
OVCC
OGND
2.2k
Ω
2.2k
Ω
VOP
VON
Figure 5. Simplified LVDS Output Architecture
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX1124EVKIT | 功能描述:数据转换 IC 开发工具 Evaluation Kit for the MAX1121 MAX1122 MAX1123 MAX1124 RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
| MAX1125 | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:8-Bit, 300Msps Flash ADC |
| MAX1125AIBH | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:8-Bit, 300Msps Flash ADC |
| MAX1125AIDO | 制造商:MAXIM 制造商全称:Maxim Integrated Products 功能描述:8-Bit, 300Msps Flash ADC |
| MAX1125BIBH | 制造商:Maxim Integrated Products 功能描述:44 PIN COUNT UCSP PACKAGE TYPE - Bulk |
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