参数资料
型号: MAX1183ECM+TD
厂商: Maxim Integrated Products
文件页数: 13/18页
文件大小: 0K
描述: IC ADC 10BIT 40MSPS DL 48-TQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,000
位数: 10
采样率(每秒): 40M
数据接口: 并联
转换器数目: 2
功率耗散(最大): 180mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-TQFP 裸露焊盘
供应商设备封装: 48-TQFP 裸露焊盘(7x7)
包装: 带卷 (TR)
输入数目和类型: 4 个单端,双极;2 个差分,双极
MAX1183
Dual 10-Bit, 40Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 2.5V, 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND, REFOUT connected to REFIN through a
10k resistor, VIN = 2VP-P (differential with respect to COM), CL = 10pF at digital outputs (Note 1), fCLK = 40MHz, TA = TMIN to TMAX,
unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (CLK, PD,
OE, SLEEP, T/B)
CLK
0.8 x
VDD
Input High Threshold
VIH
PD,
OE, SLEEP, T/B
0.8 x
OVDD
V
CLK
0.2 x
VDD
Input Low Threshold
VIL
PD,
OE, SLEEP, T/B
0.2 x
OVDD
V
Input Hysteresis
VHYST
0.1
V
IIH
VIH = OVDD or VDD (CLK)
±5
Input Leakage
IIL
VIL = 0V
±5
A
Input Capacitance
CIN
5pF
DIGITAL OUTPUTS (D9A–D0A, D9B–D0B)
Output Voltage Low
VOL
ISINK = -200A
0.2
V
Output Voltage High
VOH
ISOURCE = 200A
OVDD
- 0.2
V
Three-State Leakage Current
ILEAK
OE = OVDD
±10
A
Three-State Leakage
Capacitance
COUT
OE = OVDD
5pF
POWER REQUIREMENTS
Analog Supply Voltage Range
VDD
2.7
3
3.6
V
Output Supply Voltage Range
OVDD
1.7
2.5
3.6
V
Operating, fINA or B = 20MHz at -0.5dBFS
40
60
Sleep mode
2.8
mA
Analog Supply Current
IVDD
Shutdown, clock idle, PD =
OE = OVDD
115
A
Operating, CL = 15pF,
fINA or B = 20MHz at -0.5dBFS
5.8
mA
Sleep mode
100
Output Supply Current
IOVDD
Shutdown, clock idle, PD =
OE = OVDD
210
A
Operating, fINA or B = 20MHz at -0.5dBFS
120
180
Sleep mode
8.4
mW
Power Dissipation
PDISS
Shutdown, clock idle, PD =
OE = OVDD
345
W
Offset
±0.2
mV/V
Power-Supply Rejection Ratio
PSRR
Gain
±0.1
%V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
tDO
Figure 3 (Note 5)
5
8
ns
Output Enable Time
tENABLE
Figure 4
10
ns
Output Disable Time
tDISABLE
Figure 4
1.5
ns
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