参数资料
| 型号： | MAX1409CAP+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 31/48页 |
| 文件大小： | 0K |
| 描述： | IC DAS 16BIT LP 20-SSOP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,000 |
| 类型： | 数据采集系统（DAS） |
| 分辨率（位）： | 16 b |
| 采样率（每秒）： | 60 |
| 数据接口： | 串行 |
| 电压电源： | 模拟和数字 |
| 电源电压： | 2.7 V ~ 3.6 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 带卷 (TR) |
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MAX1407/MAX1408/MAX1409/MAX1414
Low-Power, 16-Bit Multichannel DAS with
Internal Reference,10-Bit DACs, and RTC
______________________________________________________________________________________
37
Applications Information
Alarm and RTC Programming
Three write operations are needed for every update of
the ALARM and RTC registers. First set the WE bit of
the Alarm/Clock_CTRL Register to 1. Update the Alarm,
RTC, and Alarm/Clock_CTRL Register with the new val-
ues, and then set the WE bit back to 0. This will avoid
collisions in setting the time.
Power-On Reset or Power-Up
At initial power-up, the MAX1407/MAX1408/MAX1409/
MAX1414 are in Standby mode. Figure 15 illustrates the
timing of various signals during initial Power-Up, Sleep
mode, and Wake-Up. tDSLP after AVDD exceeds +2.7V,
RESET goes high. tDFON after RESET goes high, FOUT
is enabled. INT is enabled to tDFI after FOUT is
enabled.
Power Modes
The MAX1407/MAX1408/MAX1409/MAX1414 have fou
distinct power modes, Sleep mode, Standby mode, Idle
mode, and Run mode. Table 9 lists the power-on status
of the various blocks of the MAX1407/MAX1408/
MAX1409/MAX1414. Each individual circuit block can
be powered up through the serial interface by writing to
the appropriate power registers.
Sleep Mode
In Sleep mode, only the crystal oscillator, RTC, data
registers, wake-up circuitry, and RESET Voltage
Monitor are powered up. Sleep mode is entered by
addressing the Sleep register through the serial inter-
face. Sleep mode preserves any data in the data regis-
ters. To exit Sleep mode, pull either WU1 or WU2 low or
address other Power mode registers (Standby, Idle,
Run, Power1, or Power2 registers). Asserting WU1 or
WU2 or the occurence of a Time of Day Alarm while in
Sleep mode places the device in Standby mode.
Standby Mode
After initial power-up or after exiting Sleep mode
through a wake-up event, the MAX1407/MAX1408/
MAX1409/MAX1414 are in Standby mode. Standby
mode can also be entered by addressing the Standby
register. In Standby mode, SHDN is high, FOUT is
enabled, the Low VDD voltage monitor and the PLL are
powered up, and INT is low. INT will return to a logic
high after the P begins writing to any register through
the serial interface (once a start bit is detected through
the serial interface).
Idle Mode
In Idle mode, only the ADC and ADC input buffers are
shutdown. All the other blocks are powered up. Enter
Idle mode by addressing the Idle register.
Run Mode
In Run mode, all the functional blocks are powered up
and the ADC is ready to start conversion. Enter Run
mode by either writing to the Run register or by individu-
ally powering up each circuit through the serial interface.
Wake-Up
Wake-Up mode is entered whenever a wake-up event,
such as an assertion of WU1 or WU2 or a time-of-day
alarm occurs. The Low VDD monitor, PLL, FOUT are
enabled, and SHDN goes high. Different from the
Standby mode, the status of the other power blocks
remains unchanged.
Analog Filtering
The digital filter does not provide any rejection close to
the harmonics of the modulator sample frequency.
However, due to the high oversampling ratio of the
MAX1407/MAX1408/MAX1409/MAX1414, these bands
occupy only a small fraction of the spectrum and most
broadband noise is filtered. Therefore, the analog filter-
ing requirements in front of the MAX1407/MAX1408/
MAX1409/MAX1414 are considerably reduced com-
pared to a conventional converter with no on-chip filter-
ing. In addition, because the part’s common-mode
rejection of 90dB extends out to several kHz, common-
mode noise susceptibility in this frequency range is
substantially reduced.
Depending on the application, it may be necessary to
provide filtering prior to the MAX1407/MAX1408/
MAX1409/MAX1414 to eliminate unwanted frequencies
the digital filter does not reject. It may also be necessary
in some applications to provide additional filtering to
ensure that differential noise signals outside the frequen-
cy band of interest do not saturate the analog modulator.
If passive components are placed in front of the
MAX1407/MAX1408/MAX1409/MAX1414 when the part
is used in unbuffered mode, ensure that the source
impedance is low enough not to introduce gain errors in
the system. This can significantly limit the amount of
passive anti-aliasing filtering that can be applied in
front of the MAX1407/MAX1408/MAX1409/MAX1414 in
unbuffered mode. However, when the part is used in
buffered mode, large source impedances will simply
result in a small DC offset error (a 1k
source resis-
tance will cause an offset error of less than 0.5V).
Therefore, where significant source impedances are
required, operate the device in buffered mode.
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