参数资料
| 型号： | MAX1494CCJ+T |
| 厂商： | Maxim Integrated |
| 文件页数： | 8/34页 |
| 文件大小： | 0K |
| 描述： | IC ADC W/LCD DRIVER 32-TQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,000 |
| 显示器类型： | LCD |
| 配置： | 7 段 + 2 个信号器 |
| 接口： | 串行 |
| 数字或字符： | A/D，4.5 位数字 |
| 电流 - 电源： | 960µA |
| 电源电压： | 2.7 V ~ 5.25 V |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-LQFP |
| 供应商设备封装： | 32-LQFP（7x7） |
| 包装： | 带卷 (TR) |
第1页第2页第3页第4页第5页第6页第7页当前第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页
3.5- and 4.5-Digit, Single-Chip ADCs
with LCD Drivers
Pin Description
MAX1492
PIN
MAX1494
NAME
FUNCTION
External Clock Input. When the EXTCLK bit in the control register is set, CLK is the
1
30
CLK
master clock input for the modulator and the filter (frequency = 4.9152MHz). When the
EXTCLK bit in the control register is reset, the internal clock is used. Connect CLK to
GND or DVDD when the internal oscillator is used.
2
3
4
5
6
31
32
1
2
3
DVDD
GND
AVDD
AIN+
AIN-
Digital Power Input. Connect DVDD to a 2.7V to 5.25V power supply. Bypass DVDD to
GND with 0.1μF and 4.7μF capacitors.
Ground
Analog Power Input. Connect AVDD to a 2.7V to 5.25V power supply. Bypass AVDD to
GND with 0.1μF and 4.7μF capacitors.
Positive Analog Input. Positive side of fully differential analog input. Bypass AIN+ to
GND with a 0.1μF or greater capacitor.
Negative Analog Input. Negative side of fully differential analog input. Bypass AIN- to
GND with a 0.1μF or greater capacitor.
Negative Reference Input. During internal reference operation, connect REF- to GND.
7
4
REF-
For external reference operation, bypass REF- to GND with a 0.1μF capacitor and set
V REF- from -2.2V to +2.2V, provided V REF+ > V REF- .
Positive Reference Input. During internal reference operation, connect a 4.7μF capacitor
8
5
REF+
from REF+ to GND. For external reference operation, bypass REF+ to GND with a 0.1μF
capacitor and set V REF+ from -2.2V to +2.2V, provided V REF+ > V REF- .
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
LOWBATT
EOC
CS
DIN
SCLK
DOUT
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
Low-Battery Input. When V LOWBATT < 2.048V (typ), the LOWBATT symbol on LCD turns
on and the LOWBATT bit latches high in the status register.
Active-Low, End-of-Conversion Logic Output. A logic-low at EOC indicates that a new
ADC result is available in the ADC result register.
Active-Low Chip-Select Input. Forcing CS low activates the serial interface.
Serial Data Input. Data present at DIN is shifted into the internal registers in response to
a rising edge at SCLK when CS is low.
Serial Clock Input. Apply an external clock to SCLK to facilitate communication through
the serial bus. SCLK can idle high or low.
Serial Data Output. DOUT presents serial data in response to register queries. Data
shifts out on the falling edge of SCLK. DOUT goes high impedance when CS is high.
LCD Segment 1 Driver
LCD Segment 2 Driver
LCD Segment 3 Driver
LCD Segment 4 Driver
LCD Segment 5 Driver
LCD Segment 6 Driver
LCD Segment 7 Driver
LCD Segment 8 Driver
LCD Segment 9 Driver
8
_______________________________________________________________________________________
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| MAX1494EVC16 | 功能描述:模数转换器 - ADC MAX1494C16 EVAL KIT RoHS:否 制造商:Texas Instruments 通道数量:2 结构:Sigma-Delta 转换速率:125 SPs to 8 KSPs 分辨率:24 bit 输入类型:Differential 信噪比:107 dB 接口类型:SPI 工作电源电压:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:VQFN-32 |
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