参数资料
型号: MAX15002ATL+T
厂商: Maxim Integrated Products
文件页数: 20/29页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM 40-TQFNEP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
PWM 型: 电压模式
输出数: 2
频率 - 最大: 2.2MHz
电源电压: 5.5 V ~ 23 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 40-WFQFN 裸露焊盘
包装: 带卷 (TR)
MAX15002
Dual-Output Buck Controller with
Tracking/Sequencing
The Type II compensator ’s mid-frequency gain
(approximately 4dB shown here) is designed to com-
pensate for the power modulator’s attenuation at the
desired crossover frequency, f CO (G E/A + G MOD = 0dB
at f CO ). In this example, the power modulator’s inherent
-20dB/dec roll-off above the ESR zero (f ESR ) is lever-
aged to extend the active regulation gain-bandwidth of
the voltage regulator. As shown in Figure 5b, the net
result is a 2x increase in the regulator’s gain bandwidth
while providing greater than 55° of phase margin (the
difference between G E/A and G MOD respective phases
at crossover, f CO ).
Other filter schemes pose their own problems. For
instance, when choosing high-quality filter capacitor(s),
e.g., MLCCs, and inductor, with minimal parasitics, the
inherent ESR zero can occur at a much higher frequen-
cy, as shown in Figure 5c.
As with the previous example, the actual gain and
phase response is overlaid on the power modulator’s
asymptotic gain response. One readily observes the
more dramatic gain and phase transition at or near the
power modulator’s resonant frequency, f LC , versus the
gentler response of the previous example. This is due to
the component’s lower parasitics (OCR and ESR) and
corresponding higher frequency of the inherent ESR
POWER MODULATOR GAIN AND PHASE
RESPONSE WITH LOW-PARASITIC
zero frequency. In this example, the desired crossover
frequency occurs below the ESR zero frequency.
In this example, a compensator with an inherent mid-
frequency double-zero response is required to mitigate
the effects of the filter’s double-pole. Such is available
with the Type III topology.
As demonstrated in Figure 5d, the Type III’s mid-fre-
quency double-zero gain (exhibiting a +20dB/dec
slope, noting the compensator’s pole at the origin) is
designed to compensate for the power modulator ’s
double-pole -40dB/dec attenuation at the desired
crossover frequency, f CO (again, G E/A + G MOD = 0dB
at f CO ). See Figure 5d.
In the above example, the power modulator’s inherent
(mid-frequency) -40dB/decade roll-off is mitigated by
the mid-frequency double zero’s +20dB/dec gain to
extend the active regulation gain-bandwidth of the volt-
age regulator. As shown in Figure 5d, the net result is
an approximate doubling in the regulator’s gain band-
width while providing greater than 60° of phase margin
(the difference between G E/A and G MOD respective
phases at crossover, f CO ).
Design procedures for both Type II and Type III com-
pensators are shown below.
POWER MODULATOR AND TYPE III COMPENSATOR
GAIN AND PHASE RESPONSE WITH LOW
40
OUTPUT CAPACITORS (MLCCs)
MAX15002 fig05c
90
80
PARASITIC OUTPUT CAPACITORS (MLCCs)
MAX15002 fig05d
270
20
0
|G MOD |
f LC
45
0
60
40
20
|G E/A |
< G E/A
f LC
203
135
68
-20
-40
< G MOD
f ESR
-45
-90
0
-20
< G MOD
f CO
|G MOD |
0
-68
-40
-135
-60
-135
-80
10
100
|G MOD |
ASYMPTOTE
1k 10k
100k
1M
-180
10M
-60
-80
10
100
1k
10k
100k
f ESR
1M
-203
-270
10M
FREQUENCY (Hz)
Figure 5c. Power Modulator Gain and Phase Response (High-
Quality COUT)
20
FREQUENCY (Hz)
Figure 5d. Power Modulator (High-Quality COUT) and Type III
Compensator Responses
Maxim Integrated
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