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| 型号： | MAX15066EWE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 15/21页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 4A 16WLP |
| 产品培训模块： | Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.606 V ~ 14.4 V |
| 输入电压： | 4.5 V ~ 16 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 500kHz |
| 电流 - 输出： | 4A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-UFBGA，WLCSP |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-WLP（2x2） |
MAX15066/MAX15166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
I L
or approximately as:
t OFF2 SKIP ? LIMIT × ? ?
= +
L × I
?
I SKIP-LIMIT
I LOAD
? 1 1 ?
V IN ? V OUT V OUT ?
× ?
? I LOAD ?
V OUT
t ON
t OFF1
t OFF2 = n x T CK
V OUT-RIPPLE
? I SKIP ? LIMIT ?
? 2 ?
I LOAD
Finally, frequency in skip mode is:
Figure 2. Skip Mode Waveform
f SKIP =
1
t ON + t OFF1 + t OFF2
Skip Mode Frequency and Output Ripple
Output ripple in skip mode is:
= V COUT ? RIPPLE ESR ? RIPPLE
V OUT ? RIPPLE
( I SKIP ? LIMIT LOAD ON +
) × t
ripple voltage (V OUT_RIPPLE ) shown in Figure 2 are cal-
? I
=
C OUT
In skip mode, the switching frequency (f SKIP ) and output + V
culated as follows:
t ON is the time needed for inductor current to reach SKIP
current limit (0.58A, typ): R ESR,COUT × ( I SKIP ? LIMIT ? I LOAD )
L × I SKIP ? LIMIT
t ON =
V IN ? V OUT
L × I SKIP ? LIMIT
t OFF1 =
?= ? I SKIP ? LIMIT ON OFF1 ) ?
× ( t
? 1 ?
L × I SKIP ? LIMIT × ? SKIP ? LIMIT ? I LOAD ?
× ?
+
? V V
V IN OUT OUT ?
? Q OUT =
[1]
t OFF1 is the time needed for inductor current to reach the
zero current limit (~0A):
V OUT [2]
During t ON and t OFF1 the output capacitor stores a
charge equal to (see Figure 2):
Q OUT + t
? 2 ?
? ?
? ? I LOAD × ( t ON + t OFF1 ) ? [3]
Combining [1], [2] and [3], and solving for D Q OUT :
? I ?
? 2 ?
? 1 1 ?
?
?
2
During t OFF2 (= n x t CK , number of clock cycles
skipped), the output capacitor loses this charge or can
approximate as:
To limit output ripple in skip mode, size C OUT based on
the above formula accordingly. All formulas above are
valid for I LOAD < I SKIP-LIMIT .
Compensation Design Guidelines
The devices use a fixed-frequency, peak current-mode
control scheme to provide easy compensation and
fast transient response. The inductor peak current is
monitored on a cycle-by-cycle basis and compared to
the COMP voltage (output of the voltage error ampli-
fier). The regulator’s duty cycle is modulated based on
the inductor’s peak current value. This cycle-by-cycle
control of the inductor current emulates a controlled cur-
rent source. As a result, the inductor’s pole frequency is
shifted beyond the gain bandwidth of the regulator.
System stability is provided with the addition of a simple
series capacitor-resistor from COMP to GND. This pole-
zero combination serves to tailor the desired response of
the closed-loop system.
The basic regulator loop consists of a power modulator
(comprising the regulator’s pulse-width modulator, slope
compensation ramp, control circuitry, MOSFETs, and
inductor), the capacitive output filter and load, an output
feedback divider, and a voltage-loop error amplifier with
its associated compensation circuitry (see Figure 3).
Maxim Integrated
t OFF2 =
? Q OUT
I LOAD
15
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