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| 型号： | MAX15066EWE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 18/21页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 4A 16WLP |
| 产品培训模块： | Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.606 V ~ 14.4 V |
| 输入电压： | 4.5 V ~ 16 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 500kHz |
| 电流 - 输出： | 4A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-UFBGA，WLCSP |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-WLP（2x2） |
MAX15066/MAX15166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
1ST ASYMPTOTE
R2 x (R1 + R2) -1 x 10 AVEA(dB)/20 x g MC x R LOAD x {1 + R LOAD x [K S x (1 – D) – 0.5] x (L x f SW ) -1 } -1
2ND ASYMPTOTE
R2 x (R1 + R2) -1 x g MV x (2 G C C ) -1 x g MC x R LOAD x {1 + R LOAD x [K S x (1 – D) – 0.5] x (L x f SW ) -1 } -1
GAIN
3RD ASYMPTOTE
R2 x (R1 + R2) -1 x g MV x (2 G C C ) -1 x g MC x R LOAD x {1 + R LOAD x [K S x (1 – D) – 0.5] x (L x f SW ) -1 } -1
x (2 G C OUT x {R LOAD-1 + [K S (1 – D) – 0.5] x (L x f SW ) -1 } -1 ) -1
4TH ASYMPTOTE
R2 x (R1 + R2) -1 x g MV x R C x g MC x R LOAD x {1 + R LOAD x [K S x (1 – D) – 0.5] x (L x f SW ) -1 } -1
x (2 G C OUT x {R LOAD-1 + [K S (1 – D) – 0.5] x (L x f SW ) -1 } -1 ) -1
3RD POLE
0.5 x f SW
2ND ZERO
(2 G C OUT ESR) -1
UNITY
1ST POLE
[2 G C C (10 AVEA(dB)/20
x g MV -1 )] -1
1ST ZERO
(2 G C C R C ) -1
f CO
FREQUENCY
2ND POLE
f PMOD *
NOTE:
R OUT = 10 AVEA(dB)/20 x g MV -1
f PMOD = [2 G C OUT x (ESR + {R LOAD -1 + [K S (1 – D) – 0.5] x (L x f SW ) -1 } -1 )] -1
WHICH FOR
ESR << {R LOAD -1 + [K S (1 – D) – 0.5] x (L x f SW ) -1 } -1
BECOMES
5TH ASYMPTOTE
R2 x (R1 + R2) -1 x g MV x R C x g MC x R LOAD x {1 + R LOAD x [K S x (1 – D) – 0.5] x (L x f SW ) -1 } -1
x [(2 G C OUT x {R LOAD-1 + [K S (1 – D) – 0.5] x (L x f SW ) -1 } -1 ) -1 x (0.5 x f SW )2 x (2 G f) -2
6TH ASYMPTOTE
R2 x (R1 + R2) -1 x g MV x R C x g MC x R LOAD x {1 + R LOAD x [K S x (1 – D) – 0.5] x (L x f SW ) -1 } -1
x ESR x {R LOAD-1 + [K S (1 – D) – 0.5] x (L x f SW ) -1 } -1 x (0.5 f SW ) 2 x (2 G f) -2
f PMOD = [2 G C OUT x {R LOAD -1 + [K S (1 – D) – 0.5] x (L x f SW ) -1 } -1 ] -1
f PMOD = (2 G C OUT x R LOAD ) -1 + [K S (1 – D) – 0.5] x (2 G C OUT x L x f SW ) -1
Figure 4. Asymptotic Loop Response of Peak Current-Mode Regulator
The dominant poles and zeros of the transfer loop gain
are shown below:
Figure 4 shows a graphical representation of the asymp-
totic system closed-loop response, including dominant
2 π × C C × 10
f P1 <<
g MV
AVEA ( dB ) /20
pole and zero locations.
The loop response’s fourth asymptote (in bold, Figure 4)
is the one of interest in establishing the desired cross-
f P2 =
? 1 ? K S × ( 1 ? D ) ? 0.5 ? ?
? R LOAD
f SW × L
? ?
f P3 = SW
=
=
f Z1
f Z2
1
2 π × C OUT ? + ? ? ?
?
f
2
1 1
2 π × C C R C 2 π × C OUT ESR
The order of pole-zero occurrences is:
f P1 < f P2 ≤ f Z1 < f CO < f P3 < f Z2
Note: Under heavy load, f P2 can approach f Z1 .
18
? 1
over frequency (and determining the compensation
component values). A lower crossover frequency pro-
vides for stable closed-loop operation at the expense of
a slower load and line transient response. Increasing the
crossover frequency improves the transient response at
the (potential) cost of system instability. A standard rule
of thumb sets the crossover frequency P 1/5 to 1/10 of
the switching frequency.
First, select the passive power components that meet
the application’s requirements. Then, choose the small-
signal compensation components to achieve the desired
closed-loop frequency response and phase margin
as outlined in the Closing the Loop: Designing the
Compensation Circuitry section .
Maxim Integrated
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