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参数资料
| 型号： | MAX15066EWE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 9/21页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 4A 16WLP |
| 产品培训模块： | Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.606 V ~ 14.4 V |
| 输入电压： | 4.5 V ~ 16 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 500kHz |
| 电流 - 输出： | 4A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-UFBGA，WLCSP |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-WLP（2x2） |
MAX15066/MAX15166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
Pin Configuration
TOP VIEW
(BUMPS ON BOTTOM)
+
GND
A1
LX
B1
BST
C1
PGOOD
D1
GND
A2
LX
B2
I.C.
C2
FB
D2
IN
A3
LX
B3
I.C.
C3
COMP
D3
IN
A4
V DD
B4
EN
C4
SS
D4
WLP
Pin Description
BUMP
A1, A2
A3, A4
B1, B2, B3
B4
C1
C2, C3
C4
D1
D2
D3
D4
NAME
GND
IN
LX
V DD
BST
I.C.
EN
PGOOD
FB
COMP
SS
FUNCTION
Ground. Connect A1 and A2 together as close as possible to the device.
Power-Supply Input. Input supply range is from 4.5V to 16V. Connect A3 and A4 together as close as
possible to the device. Bypass IN to GND with a minimum 22 F F ceramic capacitor as close as
possible to the device.
Inductor Connection. Connect an inductor between LX and the regulator output. LX is high
impedance when the device is in shutdown mode. Connect all LX nodes together as close as possible
to the device.
Internal 5V LDO Output. V DD powers the internal analog core. Connect a minimum of 1 F F ceramic
capacitor from V DD to GND.
High-Side MOSFET Driver Supply. Bypass BST to LX with a 0.01 F F capacitor. BST is internally
connected to the V DD regulator through a pMOS switch.
Internal Connection. Leave unconnected.
Enable Input. Connect EN to GND to disable the device. Set EN to above 1.9V (typ) to enable the
device. EN can be shorted to IN for always-on operation.
Power-Good Output. PGOOD is an open-drain output that goes high impedance when V FB exceeds
0.56V (typ). PGOOD is internally pulled low when V FB falls below 0.545V (typ). PGOOD is internally
pulled low when the device is in shutdown mode, V DD is below the UVLO threshold, or the device is in
thermal shutdown.
Feedback Input. Connect FB to the center tap of an external resistor-divider from the output to GND to
set the output voltage from 0.606V to 90% of V IN .
Voltage-Error Amplifier Output. Connect the necessary compensation network from COMP to GND
(see the Compensation Design section).
Soft-Start Timing Capacitor Connection. Connect a capacitor from SS to GND to set the startup time
(see the Setting the Soft-Start Time section).
Maxim Integrated
9
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