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参数资料
| 型号： | MAX15066EWE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 17/21页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 4A 16WLP |
| 产品培训模块： | Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.606 V ~ 14.4 V |
| 输入电压： | 4.5 V ~ 16 V |
| PWM 型： | 电流模式 |
| 频率 - 开关： | 500kHz |
| 电流 - 输出： | 4A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-UFBGA，WLCSP |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-WLP（2x2） |
MAX15066/MAX15166
High-Efficiency, 4A, Step-Down DC-DC
Regulators with Internal Power Switches
f PMOD =
? K S × ( 1 ? D ) ? 0.5
?
? ? ? ? ?
? ESR + ?
2 π × C OUT × +
? R LOAD SW × L
? ?
Q C =
f SAMPLING = SW
As previously mentioned, the power modulator’s dominate
pole is a function of the parallel effects of the load resis-
tance and the current-loop gain’s equivalent impedance:
1
? ? 1 ?
1 ?
? f ? ?
? ?
? ?
Knowing that the ESR is typically much smaller than the
parallel combination of the load and the current loop,
where the sampling effect quality factor, Q C , is:
1
π × ? ? K S × ( 1 ? D ) ? 0.5 ? ?
and the resonant frequency is:
w SAMPLING (s) = π × f SW
or:
f
2
? K S × ( ) ? 0.5 ? ?
?
1 ? D
+ ? ? ?
ESR << ?
? R LOAD SW × L
? ?
f PMOD ≈
? 1 ? K S × ( 1 ? D ) ? 0.5 ? ?
? R LOAD SW × L
? ?
R2 ( sC FF R1 + 1
? ? sC FF ( ) + 1 ? ?
= ×
e.g.,:
1
This can be expressed as:
? 1
f ?
1
2 π × C OUT × ? + ? ? ?
f ?
? 1
Having defined the power modulator’s transfer function,
the total system transfer can be written as follows
(Figure 3):
Gain(s) = G FF (s) × G EA (s) × G MOD (DC) ×
G FILTER (s) × G SAMPLING (s)
where:
R1 + R2 R1|| R2
1 ? K S × ( 1 ? D ) ? 0.5 ?
G FF ( s ) =
f PMOD ≈ + ? ?
2 π × C OUT × R LOAD 2 π × f SW × L × C OUT
Note: Depending on the application’s specifics, the
Leaving C FF empty, G FF (s) becomes:
R2
R1 + R2
Also:
? ? AVEA(dB)/20 ? ?
? sC C C +
? + 1 ?
? R
g MV
? ?
? ?
? ?
amplitude of the slope compensation ramp could have a
significant impact on the modulator’s dominate pole. For
G EA ( s )
low duty-cycle applications, it provides additional damp- = 10 AVEA(dB)/20 ×
ing (phase lag) at/near the crossover frequency. See the
Closing the Loop: Designing the Compensation Circuitry
section. There is no equivalent effect on the power
( sC C R C + 1 )
10
? ?
modulator zero:
= ZESR
f ZMOD f =
1
2 π × C OUT × ESR
If R C << 10
AVEA(dB)/20
MV
, the equation simplifies to:
G SAMPLING ( s ) =
s
s
+ + 1
π × f SW × Q C
( π × f SW )
( sC C R C + 1
= 10 AVEA(dB)/20 ×
? 10 AVEA(dB)/20 ?
? sC C ? ? + 1 ?
g MV
? ? ? ?
? ?
( sC OUT ESR + 1 )
G = R LOAD ×
? K S × ( 1 ? D ) ? 0.5 ?
? ? ? ?
? sC
+ 1 ?
+ ? ? ?
?
?
? ? 2 π × R LOAD
2 π × f SW × L
? ?
The effect of the inner current loop at higher frequencies
is modeled as a double-pole (complex conjugate)
frequency term, G SAMPLING (s), as shown:
1
2
2
Maxim Integrated
?
? ? ?
OUT ?
? ?
1
? ?
? ? 1 ?
17
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