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参数资料
| 型号： | MAX1531ETJ/V+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 31/33页 |
| 文件大小： | 0K |
| 描述： | IC PS CTRLR MULTI-OUTPUT 32WQFN |
| 标准包装： | 2,500 |
| 应用： | 五路电源监控器 |
| 电源电压： | 4.5 V ~ 28 V |
| 电流 - 电源： | 1.7mA |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-WFQFN 裸露焊盘 |
| 供应商设备封装： | 32-TQFN-EP（5x5） |
| 包装： | 带卷 (TR) |
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Multiple-Output Power-Supply Controllers for
LCD Monitors
4) Next, calculate the pole set by each linear regula-
tor ’s feedback resistance and the capacitance
(C FBL_ ) between FBL_ and AGND (approximately
5pF including stray capacitance):
(islands) together at only one location, which is a
via connected to the backside pad of the device.
All voltage-feedback dividers should be connected
to the analog ground island. The step-down regula-
tor’s input and output capacitors, and the charge
f POLE ( FBL 1 ) =
f POLE ( FBL 2 ) =
1
2 π C FBL 1 ( R 9 || R 10 )
1
2 π C FBL 2 ( R 18 || R 19 )
pump components should be a wide power ground
plane. The power ground plane should be connect-
ed to the power ground pin (PGND) with a wide
trace. Maximizing the width of the power ground
traces improves efficiency, and reduces output
f POLE ( FBL 3 ) =
f POLE ( FBL 4 ) =
f POLE ( FBL 5 ) =
1
2 π C FBL 3 ( R 25 || R 26 )
1
2 π C FBL 4 ( R 22 || R 23 )
1
2 π C FBL 5 ( R 28 || R 29 )
and
voltage ripple and noise spikes. All other ground
connections, such as the VL and IN pin bypass
capacitor and the linear regulator output capaci-
tors, should be star-connected to the backside of
the device with wide traces. Make no other connec-
tions between these separate ground planes.
3) Place the IN pin and VL pin bypass capacitors
within 5mm from the IC and connect them to their
5) Next, calculate the zero caused by the output
capacitor’s ESR:
respective pins with short, direct connections.
4) Since both MOSFETs are used for current sensing,
care must be taken to ensure that noise and DC
f ESR _ ZERO =
1
2 π C LR R ESR
errors do not corrupt the sense signals. Place both
MOSFETs close to the IC. Connect PGND to the
source of the low-side MOSFET with a short, wide
where R ESR is the equivalent series resistance of C LR .
6) To ensure stability, choose C LR large enough so that
the crossover occurs well before the poles and zero
calculated in steps 2) to 5). The poles in steps 3)
and 4) generally occur at several megahertz and
using ceramic capacitors ensures the ESR zero
occurs at several megahertz as well. Placing the
crossover below 500kHz is sufficient to avoid the
amplifier-delay pole and generally works well, unless
unusual component choices or extra capacitances
move the other poles or zero below 1MHz.
PC Board Layout and Grounding
Careful PC board layout is important for proper opera-
tion. Use the following guidelines for good PC board
layout:
1) Place the high-power components of the step-down
regulator (input capacitors, MOSFETs, inductor,
and output capacitors) first, with any grounded
connections adjacent. Connect these components
with short, wide traces. Avoid using vias in the
high-current paths. If vias are unavoidable, use
many vias in parallel to reduce resistance and
inductance.
2) Create islands for the analog ground (AGND),
power ground (PGND), and individual linear regula-
tor grounds. Connect all these ground areas
trace. Connect DL to the gate of the low-side MOS-
FET with a short, wide trace. Ensure that the traces
from DL to low-side MOSFET to PGND total no
more than 50 squares. Connect LX close to the
connection point between the low-side and high-
side MOSFETs with a short, wide trace. Connect
DH to the gate of the high-side MOSFET with a
short, wide trace. Ensure that the traces from DH to
high-side MOSFET to LX total no more than 50
squares (50 squares corresponds to 20 mils wide if
the total trace is 1in long).
5) Place all feedback voltage-divider resistors as
close to their respective feedback pins as possible.
The divider’s center trace should be kept short.
Placing the resistors far away causes their FB
traces to become antennas that can pick up
switching noise. Care should be taken to avoid run-
ning any feedback trace near LX or the switching
nodes in the charge pumps.
6) Minimize the length and maximize the width of the
traces between the output capacitors and the load
for best transient responses.
7) Minimize the size of the LX node while keeping it
wide and short. Keep the LX node away from feed-
back nodes and analog ground. Use DC traces as
shield if necessary.
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