参数资料
型号: MAX16065ETM+
厂商: Maxim Integrated Products
文件页数: 37/62页
文件大小: 0K
描述: IC SYSTEM MANAGER 12CH 48-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 43
应用: 电源监控器,序列发生器
电源电压: 2.8 V ~ 14 V
电流 - 电源: 4.5mA
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-WFQFN 裸露焊盘
供应商设备封装: 48-TQFN-EP(6x6)
包装: 管件
12-Channel/8-Channel, Flash-Configurable System
Managers with Nonvolatile Fault Registers
The normal watchdog timeout period, t WDI , begins after
the first transition on WDI before the conclusion of the
long startup watchdog period, t WDI_STARTUP (Figure 8).
During the normal operating mode, WDO asserts if the
F P does not toggle WDI with a valid transition (high-to-
low or low-to-high) within the standard timeout period,
t WDI . WDO remains asserted until WDI is toggled or
RESET is asserted (Figure 9).
While EN is low, the watchdog timer is in reset. The
watchdog timer does not begin counting until the power-
on mode is reached and RESET is deasserted. The
watchdog timer is reset and WDO deasserts any time
RESET is asserted (Figure 10). The watchdog timer will
be held in reset while RESET is asserted.
V TH
LAST MON_
WDI
The watchdog can be configured to control the RESET
output as well as the WDO output. RESET asserts for
the reset timeout, t RP , when the watchdog timer expires
and the Watchdog Reset Output Enable bit (r76h[7]) is
set to ‘1.’ When RESET is asserted, the watchdog timer
is cleared and WDO is deasserted, therefore, WDO
pulses low for a short time (approximately 1 F s) when
the watchdog timer expires. RESET is not affected by
the watchdog timer when the Watchdog Reset Output
Enable bit (r76h[7]) is set to ‘0.’ If a RESET is asserted
by the watchdog timeout, the WDRESET bit is set to ‘1.’ A
connected processor can check this bit to see the reset
was due to a watchdog timeout. See Table 24 for more
information on configuring watchdog functionality.
< t WDI
t WDI_STARTUP
< t WDI
t RP
RESET
Figure 8. Normal Watchdog Startup Sequence
V CC
WDI
< t WDI
< t WDI
< t WDI
> t WDI
< t WDI
< t WDI
< t WDI
0V
t WDI
V CC
WDO
0V
Figure 9. Watchdog Timer Operation
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