参数资料
型号: MAX16955AUE/V+
厂商: Maxim Integrated Products
文件页数: 20/26页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 16TSSOP
其它有关文件: Automotive Product Guide
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 96
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1MHz
电源电压: 3.5 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
eliminates the double pole in the feedback loop caused
by the inductor and output capacitor, resulting in a
smaller phase shift and requiring less elaborate error-
amplifier compensation than voltage-mode control. A
simple single-series resistor (R C ) and capacitor (C C )
are required to have a stable, high-bandwidth loop in
applications where ceramic capacitors are used for
output filtering (Figure 5). For other types of capacitors,
due to the higher capacitance and ESR, the frequency
of the zero created by the capacitance and ESR is
lower than the desired closed-loop crossover frequen-
cy. To stabilize a nonceramic output capacitor loop,
add another compensation capacitor (C F ) from COMP
to SGND to cancel this ESR zero.
The basic regulator loop is modeled as a power modu-
lator, output feedback divider, and an error amplifier.
The power modulator has a DC gain set by g mc ×
R LOAD , with a pole and zero pair set by R LOAD , the out-
The feedback voltage-divider has a gain of GAIN FB =
V FB /V OUT , where V FB is 1V (typ).
The transconductance error amplifier has a DC gain of
GAIN EA(dc) = g m,EA × R OUT,EA , where g m,EA is the
error amplifier transconductance, and R OUT,EA is the
output resistance of the error amplifier. Use g m,EA of
2500μS (max) and R OUT,EA of 30M Ω (typ) for compen-
sation design with the highest phase margin.
A dominant pole (f dpEA ) is set by the compensation
capacitor (C C ), the compensation resistor (R C ), and the
amplifier output resistance (R OUT,EA ). A zero (f zEA ) is
set by the compensation resistor (R C ) and the compen-
sation capacitor (C C ). There is an optional pole (f pEA )
set by C F and R C to cancel the output capacitor ESR
zero if it occurs near the crossover frequency (f C ,
where the loop gain equals 1 (0dB)).
Thus:
put capacitor (C OUT ), and its ESR. The following equa-
tions determine the approximate value for the gain of
the power modulator (GAIN MOD(dc) ), neglecting the
effect of the ramp stabilization. Ramp stabilization is
f dpEA =
1
2 π × C C × ( R OUT , EA + R C )
necessary when the duty cycle is above 50% and is
internally and automatically done for the MAX16955:
GAIN MOD ( dc ) ? g mc × R LOAD
f zEA =
1
2 π × C C × R C
f pEA =
f pMOD C ≤ SW
<< f
f pMOD =
f zMOD =
GAIN MOD ( ) ×
× GAIN EA ( ) = 1
V OUT
where R LOAD = V OUT /I OUT(MAX) in Ω, f SW is the switch-
ing frequency in MHz, L is the output inductance in μH,
and g mc = 1/(A V_CS × R DC ) in S. A V_CS is the voltage
gain of the current-sense amplifier and is typically
11V/V (see the Electrical Characteristics table). R DC is
the DC-resistance of the inductor or the current-sense
resistor in Ω .
In a current-mode step-down converter, the output
capacitor, its ESR, and the load resistance introduce a
pole at the following frequency:
1
2 π × C OUT × R LOAD
The output capacitor and its ESR also introduce a zero at:
1
2 π × ESR × C OUT
1
2 π × C F × R C
The loop-gain crossover frequency (f C ) should be set
below 1/5 the switching frequency and much higher
than the power-modulator pole (f pMOD ):
f
5
The total loop gain as the product of the modulator
gain, the feedback voltage-divider gain, and the error
amplifier gain at f C should be equal to 1. So:
V FB
fC fC
For the case where f zMOD is greater than f C :
When C OUT is composed of n identical capacitors in
parallel, the resulting C OUT = n × C OUT(EACH) , and ESR
= ESR (EACH) /n. Note that the capacitor zero for a paral-
lel combination of like capacitors is the same as for an
individual capacitor.
20
GAIN EA ( fC ) = g m , EA × R C
GAIN MOD ( fC ) = GAIN MOD ( dc ) ×
f pMOD
f C
Maxim Integrated
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