参数资料
型号: MAX16955AUE/V+
厂商: Maxim Integrated Products
文件页数: 23/26页
文件大小: 0K
描述: IC REG CTRLR BUCK PWM CM 16TSSOP
其它有关文件: Automotive Product Guide
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 96
PWM 型: 电流模式
输出数: 1
频率 - 最大: 1MHz
电源电压: 3.5 V ~ 36 V
降压:
升压:
回扫:
反相:
倍增器:
除法器:
Cuk:
隔离:
工作温度: -40°C ~ 125°C
封装/外壳: 16-TSSOP(0.173",4.40mm)裸露焊盘
包装: 管件
MAX16955
36V, 1MHz Step-Down Controller
with Low Operating Current
To estimate the temperature rise of the die, use the fol-
lowing equation:
T J = T A + (P T × θ JA )
where θ JA is the junction-to-ambient thermal resistance
of the package, P T is power dissipated in the device,
and T A is the ambient temperature. The θ JA is 38.3°C/W
for the 16-pin TSSOP package on multilayer boards,
with the conditions specified by the respective JEDEC
standards (JESD51-5, JESD51-7). If actual operating
conditions significantly deviate from those described in
the JEDEC standards, then an accurate estimation of
the junction temperature requires a direct measurement
of the case temperature (T C ). Then, the junction temper-
ature can be calculated using the following equation:
T J = T C + (P T × θ JC )
Use 3°C/W as θ JC thermal resistance for the 16-pin
TSSOP package. The case-to-ambient thermal resis-
tance ( θ CA ) is dependent on how well the heat is trans-
ferred from the PCB to the ambient. Therefore, solder
the exposed pad of the TSSOP package to a large
copper area to spread heat through the board surface,
minimizing the case-to-ambient thermal resistance. Use
large copper areas to keep the PCB temperature low.
Applications Information
PCB Layout Guidelines
Make the controller ground connections as follows: cre-
ate a small analog ground plane near the IC by using
any of the PCB layers. Connect this plane to SGND and
use this plane for the ground connection for the SUP
bypass capacitor, compensation components, feed-
back dividers, and FOSC resistor.
Maxim Integrated
If possible, place all power components on the top side
of the board and run the power stage currents, espe-
cially large high-frequency components, using traces or
copper fills on the top side only, without adding vias.
On the top side, lay out a large PGND copper area for
the output, and connect the bottom terminals of the
high-frequency input capacitors, output capacitors, and
the source terminals of the low-side MOSFET to that
area.
Then, make a star connection of the SGND plane to the
top copper PGND area with few vias in the vicinity of
the source terminal sensing. Do not connect PGND and
SGND anywhere else. Refer to the MAX16955 evalua-
tion kit data sheet for guidance.
Keep the power traces and load connections short,
especially at the ground terminals. This practice is
essential for high efficiency and jitter-free operation. Use
thick copper PCBs (2oz. vs. 1oz.) to enhance efficiency.
Place the controller IC adjacent to the synchronous
rectifier MOSFET (NL) and keep the connections for LX,
PGND, DH, and DL short and wide. Use multiple small
vias to route these signals from the top to the bottom
side. The gate current traces must be short and wide,
measuring 50 mils to 100 mils wide if the low-side
MOSFET is 1in from the controller IC. Connect the
PGND trace from the IC close to the source terminal of
the low-side MOSFET.
Route high-speed switching nodes (BST, LX, DH, and
DL) away from the sensitive analog areas (FOSC,
COMP, and FB). Group all SGND-referred and feed-
back components close to the IC. Keep the FB and
compensation network nets as small as possible to pre-
vent noise pickup.
23
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