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参数资料
| 型号： | MAX17480EVKIT+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 44/48页 |
| 文件大小： | 0K |
| 描述： | EVALUATION KIT FOR MAX17480 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 主要目的： | DC/DC，步降 |
| 输出及类型： | 3，非隔离 |
| 输入电压： | 4 ~ 26 V |
| 稳压器拓扑结构： | 降压 |
| 板类型： | 完全填充 |
| 已供物品： | 板 |
| 已用 IC / 零件： | MAX17480 |
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AMD 2-/3-Output Mobile Serial
VID Controller
SVD
SVC
S
P
START
CONDITION
DATA LINE
STABLE
DATA VALID
CHANGE
OF DATA
ALLOWED
STOP
CONDITION
Figure 12. SVI Bus START, STOP, and Data Change Conditions
DATA OUTPUT
BY MASTER
D7
D6
D0
NOT ACKNOWLEDGE
DATA OUTPUT
BY MAX17480
ACKNOWLEDGE
SVC FROM
MASTER
1
CLK1
2
CLK2
8
CLK8
9
CLK9
S
START
CONDITION
ACKNOWLEDGE
CLOCK PULSE
Figure 13. SVI Bus Acknowledge
Bus Not Busy
The SVI bus is not busy when both data and clock lines
remain high. Data transfers can be initiated only when
the bus is not busy. Figure 13 shows the SVI bus
acknowledge.
Start Data Transfer (S)
Starting from an idle bus state (both SVC and SVD are
high), a high-to-low transition of the data (SVD) line while
the clock (SVC) is high determines a START condition.
All commands must be preceded by a START condition.
Stop Data Transfer (P)
A low-to-high transition of the SDA line while the clock
(SVC) is high determines a STOP condition. All opera-
tions must be ended with a STOP condition.
Slave Address
After generating a START condition, the bus master
transmits the slave address consisting of a 7-bit device
code (110xxxx) for the MAX17480. Since the
MAX17480 is a write-only device, the eighth bit of the
slave address is 0. The MAX17480 monitors the bus for
its corresponding slave address continuously. It gener-
ates an acknowledge bit if the slave address was true
and it is not in a programming mode.
SVD Data Valid
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the high period of the clock signal. The data
on the line must be changed during the low period of
the clock signal. There is one clock pulse per bit of data.
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse that is associated with this acknowledge bit. The
device that acknowledges has to pull down the SVD
line during the acknowledge clock pulse so that the
SVD line is stable low during the high period of the
acknowledge-related clock pulse. Of course, setup and
hold times must be taken into account. See Figure 13.
44
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相关代理商/技术参数 |
参数描述 |
|---|---|
| MAX17480EVKIT+ | 功能描述:电源管理IC开发工具 MAX17480 Eval Kit RoHS:否 制造商:Maxim Integrated 产品:Evaluation Kits 类型:Battery Management 工具用于评估:MAX17710GB 输入电压: 输出电压:1.8 V |
| MAX17480GTL+ | 功能描述:显示驱动器和控制器 2-/3-Output Mobile erial VID Ctlr RoHS:否 制造商:Panasonic Electronic Components 工作电源电压:2.7 V to 5.5 V 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Reel |
| MAX17480GTL+T | 功能描述:显示驱动器和控制器 2-/3-Output Mobile erial VID Ctlr RoHS:否 制造商:Panasonic Electronic Components 工作电源电压:2.7 V to 5.5 V 最大工作温度: 安装风格:SMD/SMT 封装 / 箱体:QFN-44 封装:Reel |
| MAX17482GTL+ | 功能描述:电压模式 PWM 控制器 NDA IC RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
| MAX17482GTL+T | 功能描述:电压模式 PWM 控制器 NDA IC RoHS:否 制造商:Texas Instruments 输出端数量:1 拓扑结构:Buck 输出电压:34 V 输出电流: 开关频率: 工作电源电压:4.5 V to 5.5 V 电源电流:600 uA 最大工作温度:+ 125 C 最小工作温度:- 40 C 封装 / 箱体:WSON-8 封装:Reel |
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