参数资料
型号: MAX17480EVKIT+
厂商: Maxim Integrated Products
文件页数: 5/48页
文件大小: 0K
描述: EVALUATION KIT FOR MAX17480
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
主要目的: DC/DC,步降
输出及类型: 3,非隔离
输入电压: 4 ~ 26 V
稳压器拓扑结构: 降压
板类型: 完全填充
已供物品:
已用 IC / 零件: MAX17480
AMD 2-/3-Output Mobile Serial
VID Controller
ELECTRICAL CHARACTERISTICS (continued)
(Circuit of Figure 2, V IN = 12V, V CC = V DD = V IN3 = SHDN = PGD_IN = 5V, V DDIO = 1.8V, OPTION = GNDS_ = AGND = PGND,
FBDC_ = FBAC_ = OUT3 = CSP_ = CSN_ = 1.2V, all DAC codes set to the 1.2V code, T A = 0°C to +85°C , unless otherwise noted.
Typical values are at T A = +25 ° C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
FAULT DETECTION
PWM mode
250
300
350
mV
Output Overvoltage Trip
Threshold
(SMPS1 and SMPS2 Only)
V OVP_
Measured at
FBDC_, rising
edge
Skip mode and output
has not reached the
regulation voltage
1.80
1.85
1.90
V
Output Overvoltage Fault
Minimum OVP
threshold
0.8
Propagation Delay (SMPS1 and
t OVP
FBDC_ forced 25mV above trip threshold
10
μs
SMPS2 Only)
Output Undervoltage Protection
Trip Threshold
Output Undervoltage Fault
Propagation Delay
V UVP
t UVP
Measured at FBDC_ or OUT3 with respect
to unloaded output voltage
FBDC_ forced 25mV below trip threshold
-450
-400
10
-350
mV
μs
Measured at
Lower threshold,
PWRGD Threshold
FBDC_ or OUT3
with respect to
unloaded output
voltage,15mV
falling edge
(undervoltage)
Upper threshold,
rising edge
-350
+150
-300
+200
-250
+250
mV
hysteresis (typ)
(overvoltage)
PWRGD Propagation Delay
PWRGD, Output Low Voltage
t PWRGD
FBDC_ or OUT3 forced 25mV outside the
PWRGD trip thresholds
I SINK = 4mA
10
0.4
μs
V
PWRGD Leakage Current
PWRGD Startup Delay and
Transition Blanking Time
I PWRGD
t BLANK
High state, PWRGD forced to 5.5V,
T A = +25°C
Measured from the time when FBDC_ and
OUT3 reach the target voltage
20
1
μA
μs
VRHOT Trip Threshold
VRHOT Delay
VRHOT , Output Low Voltage
VRHOT Leakage Current
THRM Input Leakage
Thermal-Shutdown Threshold
t VRHOT
T SHDN
Measured at THRM, with respect to V CC ,
falling edge, 115mV hysteresis (typ)
THRM forced 25mV below the VRHOT trip
threshold, falling edge
I SINK = 4mA
High state, VRHOT forced to 5V, T A = +25°C
T A = +25°C
Hysteresis = 15°C
29.5
-100
30
10
+160
30.5
0.4
1
+100
%
μ S
V
μA
nA
°C
GATE DRIVERS
DH_ Gate-Driver On-Resistance
DL_ Gate-Driver On-Resistance
R ON(DH _ )
R ON(DL _ )
BST_ - LX_ forced
to 5V (Note 4)
DL_, high state
DL_, low state
High state (pullup)
Low state (pulldown)
0.9
0.7
0.7
0.25
2.5
2.5
2.0
0.6
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5
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