参数资料
型号: MAX1889ETE+T
厂商: Maxim Integrated Products
文件页数: 22/32页
文件大小: 0K
描述: IC PWR SUP TRPL LCD 16-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 控制器,TFT LCD
输入电压: 2.7 V ~ 5.5 V
输出数: 3
输出电压: 2.7 V ~ 13 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-WQFN 裸露焊盘
供应商设备封装: 16-TQFN-EP(5x5)
包装: 带卷 (TR)
Triple-Output TFT LCD Power Supply
with Fault Protection
I LOAD ( MAX ) = ? I DRV - BE ? β MIN
I DRIVE ( MIN ) =
The transistor ’ s current gain limits the guaranteed maxi-
mum output current to:
? V ?
? R BE ?
where I DRV is the minimum base-drive current, and R BE
is the pullup resistor connected between the transis-
tor ’ s base and emitter. Furthermore, the transistor ’ s cur-
rent gain increases the linear regulator ’ s DC loop gain
(see the Stability Requirements section), so excessive
gain destabilizes the output. Therefore, transistors with
current gain over 100 at the maximum output current
are not recommended. The transistor ’ s input capaci-
tance and input resistance also create a second pole,
which could be low enough to make the output unsta-
ble when heavily loaded.
During startup, the LDO outputs are below their respec-
tive setpoints, and the base drive to the pass transis-
tors is a maximum. The large drive currents can cause
the charge-pump outputs to collapse. If the charge-
pump loading is objectionable, base resistors can be
added between the drive outputs (DRVN and DRVP)
and the pass transistors (Figure 7). These resistors limit
the maximum drive current and prevent discharging the
charge pump ’ s output capacitors. Select the minimum
base drive current to meet the maximum required LDO
output current:
I LDOOUT(MAX)
β MIN
The resistance required to guarantee this base current is:
The transistor ’ s saturation voltage at the maximum output
current determines the minimum input-to-output voltage
differential that the linear regulator supports.
Alternatively, the package ’ s power dissipation could limit
the usable maximum input-to-output voltage differential.
The maximum power dissipation capability of the transis-
R BASE ≤
=
V LDOIN ( MAX ) - V BE
I DRIVE ( MIN )
β MIN ( V LDOIN ( MAX ) - V BE
I LDOOUT ( MAX )
)
tor ’ s package and mounting must exceed the actual
power dissipation in the device. The power dissipation
equals the maximum load current times the maximum
input-to-output voltage differential:
P = I LOAD ( MAX ) ( V LDOIN - V LDOOUT ) =
I LOAD ( MAX ) V CE
V N
C24
2200pF
As a consequence of adding the base resistors, a volt-
age change at DRVN and DRVP accompanies changes
in drive current. This voltage change can be coupled
through parasitic capacitance to the LDO feedback
pins. If the rate of voltage change is sufficiently large, it
can cause instability.
V P
C20
470pF
MAX1889
V NL
Q1
R19
15k ?
7
6
DRVN
FBN
DRVP
FBP
8
9
R20
51k ?
Q2
V PL
REF
Figure 7. Limiting LDO Drive Current During Startup
22
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