参数资料
型号: MAX1889ETE+T
厂商: Maxim Integrated Products
文件页数: 25/32页
文件大小: 0K
描述: IC PWR SUP TRPL LCD 16-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 控制器,TFT LCD
输入电压: 2.7 V ~ 5.5 V
输出数: 3
输出电压: 2.7 V ~ 13 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-WQFN 裸露焊盘
供应商设备封装: 16-TQFN-EP(5x5)
包装: 带卷 (TR)
Triple-Output TFT LCD Power Supply
with Fault Protection
Additional Application Circuits
Operation with Output Voltage >13V
The maximum output voltage of the step-up regulator is
13V, which is limited by the absolute maximum rating of
the internal power MOSFET. To achieve higher output
voltage, an external N-channel MOSFET can be cas-
coded with the internal FET (Figure 9). Since the gate of
the external FET is biased from the input supply, use a
logic-level FET to ensure that the FET is fully enhanced
at the minimum input voltage. The current rating of the
FET needs to be higher than the internal current limit.
Changing Power-Up Sequence
The power-up sequencing of the linear regulators can be
controlled using external delays. Figure 10 shows an
application where the negative linear-regulator output
powers up with a certain delay after the positive linear
regulator reaches regulation. The resistors R1, R2, and
the capacitor C form an RC network that provides the
power-up delay. The time constant of this RC network is:
V N
V IN
STEP-UP
REGULATOR
LX
FB
PGND
V P
V MAIN
15V
τ=
R1 × R2
R 1 + R 2
C
MAX1889
Select the ratio of R1 and R2 so that:
Figure 9. Operation with Output Voltage >13V Using Cascoded
V N
R 2
R 1 + R 2
+ V PL
R 1
R 1 + R 2
= 0
MOSFET
The required RC time constant is:
= - N
20 + 9 ?
?
?
or:
R 1 V
R 2 V PL
With this R1/R2 ratio, the power-up delay can be calcu-
τ=
4 ms
? 9 ?
? 20 ?
ln ?
? 0 . 7 - 0 . 125 ?
? ?
= 1 . 68 ms
? R 1 ?
? PL R 1 + R 2 ?
?
?
lated as:
V
τ D = τ ln ? V - 0 . 125 V ?
? D ?
Choose C = 0.1μF, then R1//R2 = 16.8k ? . Use stan-
dard resistor values: R1 = 56k ? and R2 = 24k ? .
Disabling Input MOSFET Switch
If the input protection MOSFET is not needed, disable
the input overcurrent comparator by connecting the
=
where V D is the forward voltage drop of the diode and
0.125V is the FBN regulation point.
As a design example, assume the positive linear-regu-
lator output V PL is +20V, the negative charge-pump
output V N is -9V, and the required power-up delay time
t D is 4ms:
R 1
The ratio of R1 and R2 should 9 be:
R 2 20
OCP pin to ground, the OCN pin to V IN . Leave the
GATE pin floating (Figure 11).
Generating Gamma Reference Voltage
The reference voltage for the Gamma correction resis-
tor string can be produced using the linear-regulator
controller. If the voltage difference between the main
boost voltage (V MAIN ) and the Gamma reference volt-
age is 400mV or greater, the emitter of the PNP pass
transistor should be connected to V MAIN .
______________________________________________________________________________________
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