参数资料
型号: MAX1997ETJ+T
厂商: Maxim Integrated Products
文件页数: 11/31页
文件大小: 0K
描述: IC PWR SUPPLY TFT LCD 32TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 控制器,TFT LCD
输入电压: 2.7 V ~ 5.5 V
输出数: 5
输出电压: 2.7 V ~ 13 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 32-WFQFN 裸露焊盘
供应商设备封装: 32-TQFN-EP(5x5)
包装: 带卷 (TR)
Quintuple/Triple-Output TFT LCD Power Supplies
with Fault Protection and VCOM Buffer
Pin Description (continued)
PIN
MAX1997 MAX1998
NAME
FUNCTION
Logic Linear-Regulator (REG 1) Feedback Input. FB1 regulates at 1.25V nominal. Connect
4
FB1
FB1 to the center tap of a resistive voltage-divider between the REG 1 output and the analog
ground (GND) to set the output voltage. Place the resistive voltage-divider close to the pin.
Sequence Timing Control Input. Connect a capacitor from this pin to GND. This timing
capacitor controls the turn-on of REG P, REG N, REG 2, and DRVA. The sequence timing
5
2
CT
block is enabled, together with the main step-up regulator, when ONDC goes high. Then an
internal 5μA current source charges the timing capacitor from 0V to V IN , which sets the turn-
on delay. A discharge switch keeps CT at GND when the sequence timing block is disabled.
(See the Power-Up Sequencing and Inrush Current Control section.)
Gate-Off Linear-Regulator (REG N) Sequence Control Input. REG N is enabled when SHDN is
6
3
ONN
high, the gate to the input P-channel MOSFET is low, ONDC is high, and V CT > V ON N . (See
the Power-Up Sequencing and Inrush Current Control section.)
Gate-On Linear-Regulator (REG P) Sequence Control Input. REG P is enabled when SHDN is
7
4
ONP
high, the gate to the input P-channel MOSFET is low, ONDC is high, and V CT > V ONP . (See
the Power-Up Sequencing and Inrush Current Control section.)
Gamma Linear-Regulator (REG 2) Sequence Control Input. REG 2 is enabled when SHDN is
high, the gate to the input P-channel MOSFET is low, ONDC is high, and V CT > V ON 2 . ON2
8
5
ON2
also controls the DRVA open-drain output, which is typically used to turn on an N-channel
MOSFET between the step-up regulator output and the source driver ICs ’ supply pins. (See
the Power-Up Sequencing and Inrush Current Control section.)
Gate-Off Linear-Regulator (REG N) Base Drive. Open drain of an internal P-channel MOSFET.
9
6
DRVN
Connect DRVN to the base of an external NPN linear regulator pass transistor. (See the Pass
Transistor Selection section.)
Gate-Off Linear-Regulator (REG N) Feedback Input. FBN regulates to 125mV nominal. Connect
10
7
FBN
FBN to the center tap of a resistive voltage-divider between the REG N output and the reference
voltage (REF) to set the output voltage. Place the resistive voltage-divider close to the pin.
Open-Drain Sequence Output. The DRVA open-drain output is controlled by ON2 . DRVA is
typically used to turn on an N-channel MOSFET between the step-up regulator output and the
11
8
DRVA
source-driver ICs ’ supply pins. DRVA is high impedance when SHDN is high, the gate to the
input P-channel MOSFET is low, ONDC is high, and V CT > V ON2 . Otherwise, DRVA connects
to ground. (See the Power-Up Sequencing and Inrush Current Control section.)
12
13
14
15
16
17
9
10
REF
GND
FBNB
OUTB
V DDB
FBPB
Internal Reference Bypass Terminal. Connect a 0.22μF ceramic capacitor from REF to the
analog ground (GND). External load capability is at least 75μA.
Analog Ground.
VCOM Buffer Inverting Input. (See the VCOM Buffer section.)
VCOM Buffer Output. Requires a minimum 0.47μF ceramic filter capacitor to GND. Place the
capacitor as close as possible to OUTB.
VCOM Buffer Supply Input. Bypass to GND with a 0.47μF capacitor as close as possible to
the pin.
VCOM Buffer Noninverting Input. (See the VCOM Buffer section.)
Gamma Linear-Regulator (REG 2) Feedback Input. FBP regulates to 1.25V nominal. Connect
18
FB2
FB2 to the center tap of a resistive voltage-divider between the REG 2 output and the analog
ground (GND) to set the output voltage. Place the divider close to the pin.
______________________________________________________________________________________
11
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