参数资料
型号: MAX3107EAG+T
厂商: Maxim Integrated Products
文件页数: 22/52页
文件大小: 0K
描述: IC UART SPI/I2C 128 FIFO 24SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
特点: 内部振荡器
通道数: 4,QUART
FIFO's: 128 字节
规程: RS232,RS485
电源电压: 2.35 V ~ 3.6 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
安装类型: 表面贴装
封装/外壳: 24-SSOP(0.209",5.30mm 宽)
供应商设备封装: 24-SSOP
包装: 标准包装
其它名称: MAX3107EAG+TDKR
SPI/I2C UART with 128-Word FIFOs
Bits 7 and 6: No Function
Bit 5: MultiDropInt
The MultiDropInt interrupt is set when the MAX3107 receives an address character in 9-bit multidrop mode
(MODE2[6] is 1). This bit is cleared when SpclCharInt is read. The SpclCharInt bit can be routed to ISR[1] by enabling
SpclChrIntEn[5].
Bit 4: BREAKInt
The BreakInt interrupt is set when a line BREAK (RX low for longer than one character length) is detected by the
receiver. This bit is cleared after SpclCharInt is read. The BREAKInt interrupt can be routed to ISR[1] by enabling
SpclChrIntEn[4].
Bit 3: XOFF2Int
The XOFF2Int interrupt bit is set when an XOFF2 special character is received and special character detection is
enabled, through MODE2[4]. This interrupt is cleared upon reading SpclCharInt. The XOFF2Int interrupt can be routed
to the ISR[1] interrupt bit, if enabled through SpclChrIntEn[3].
Bit 2: XOFF1Int
The XOFF1Int interrupt bit is set when an XOFF1 special character is received and special character detection is
enabled, through MODE2[4]. This interrupt is cleared upon reading SpclCharInt. The XOFF1Int interrupt can be routed
to the ISR[1] interrupt bit, if enabled through SpclChrIntEn[2].
Bit 1: XON2Int
The XON2Int interrupt bit is set when an XON2 special character is received and special character detection is
enabled, through MODE2[4]. This interrupt is cleared upon reading SpclCharInt. The XON2Int interrupt can be routed
to the ISR[1] interrupt bit, if enabled through SpclChrIntEn[1].
Bit 0: XON1Int
The XON1Int interrupt bit is set when an XON1 special character is received and special character detection is
enabled, through MODE2[4]. This interrupt is cleared upon reading SpclCharInt. The XON1Int interrupt can be routed
to the ISR[1] interrupt bit, if enabled through SpclChrIntEn[0].
SpclCharInt—Special Character Interrupt Register
ADDRESS:
0x06
MODE:
COR
BIT
7
6
5
4
3
2
1
0
NAME
MultiDropInt
BREAKInt
XOFF2Int
XOFF1Int
XON2Int
XON1Int
RESET
0
Maxim Integrated
29
MAX3107
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