参数资料
型号: MAX3107EAG+T
厂商: Maxim Integrated Products
文件页数: 37/52页
文件大小: 0K
描述: IC UART SPI/I2C 128 FIFO 24SSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 1
特点: 内部振荡器
通道数: 4,QUART
FIFO's: 128 字节
规程: RS232,RS485
电源电压: 2.35 V ~ 3.6 V
带自动流量控制功能:
带IrDA 编码器/解码器:
带故障启动位检测功能:
安装类型: 表面贴装
封装/外壳: 24-SSOP(0.209",5.30mm 宽)
供应商设备封装: 24-SSOP
包装: 标准包装
其它名称: MAX3107EAG+TDKR
SPI/I2C UART with 128-Word FIFOs
Bits 7 and 6: No Function
Bit 5: 4xMode
When the 4xMode bit is set high, the MAX3107 baud rate is quadruple the regular (16x sampling) baud rate. The
2xMode bit should be set low if 4xMode is enabled. See the 2x and 4x Rate Modes section for more information.
Bit 4: 2xMode
When the 2xMode bit is set high, the MAX3107 baud rate is double the regular (16x sampling) baud rate. See the 2x
and 4x Rate Modes section for a detailed description.
Bits 3–0: FRACT[3:0]
This is the fractional portion of the baud-rate generator divisor. Set FRACT[3:0] to zero if not used. See the Fractional
Baud-Rate Generator section for calculations.
DIVLSB and DIVMSB define the baud-rate generator integer divisors. The minimum value is 1. See the Fractional Baud
Rate Generator section for more information.
Bits 7–0: Div[7:0]
Div[7:0] are the 8 LSBs of the integer divisor portion (DIV) of the baud-rate generator.
Bits 7–0: Div[15:8]
Div[15:8] is the MSB portion of the integer divisor (DIV).
BRGConfig—Baud-Rate Generator Configuration Register
DIVLSB—Baud-Rate Generator LSB Divisor Register
DIVMSB—Baud-Rate Generator MSB Divisor Register
ADDRESS:
0x1B
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
4xMode
2xMode
FRACT3
FRACT2
FRACT1
FRACT0
RESET
0
ADDRESS:
0x1C
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
Div7
Div6
Div5
Div4
Div3
Div2
Div1
Div0
RESET
0
1
ADDRESS:
0x1D
MODE:
R/W
BIT
7
6
5
4
3
2
1
0
NAME
Div15
Div14
Div13
Div12
Div11
Div10
Div9
Div8
RESET
0
42
Maxim Integrated
MAX3107
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