参数资料
型号: MAX5040EUB+T
厂商: Maxim Integrated Products
文件页数: 15/21页
文件大小: 0K
描述: IC CNTRLR VOLT TRACK 10-UMAX
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
应用: 处理器
电流 - 电源: 1.3mA
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-µMAX
包装: 带卷 (TR)
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
NORMALIZED THERMAL TRANSIENT IMPEDANCE, JUNCTION TO AMBIENT
2
1
DUTY CYCLE = 0.5
0.2
NOTES:
0.1
0.1
0.05
P DM
t 1
0.02
t 2
1. DUTY CYCLE, D =
t 1
t 2
2. PER UNIT BASE = R thJA = + 70 ° C/W
SINGLE PULSE
3. T JM - T A = P DM Z thJA (t)
4. SURFACE MOUNTED
0.01
0.0001
0.001
0.01
0.1
1
10
100
600
SQUARE WAVE PULSE DURATION (s)
Figure 12. Normalized Thermal Transient Impedance
From step 5: the maximum V I/O and V CORE differential
voltage = (I CORE(LIM) ) x (R DS(ON) ) = 6A x 0.04 ? x 1.5
= 360mV.
From step 6 (first bullet): power dissipation = I PSLIM 2 x
R DS(ON) = (6A) 2 x 0.04 ? x 1.5 = 2.16W.
From step 6 (second bullet): power dissipation = (V I/O -
V CORE ) x I CORE = (3.3V - 1.8V) x 4A = 6W.
From step 6 (third bullet): power dissipation = I I/O 2 x
R DS(ON) = (3A) 2 x 0.04 ? x 1.5 = 0.54W.
So, the worst-case power dissipation in the MOSFET is
6W for a maximum duration of 20ms. From the
Si9428DY data sheet, under the normalized thermal
transient impedance curve (Figure 12), the Z θ JA is 0.05
x +70°C/W for a single pulse. The worst-case junction
To calculate the high-side limit, set the maximum CORE
voltage set point at the minimum system CORE voltage
minus the total system tolerance:
CORESET MAX = CORE MIN - TOL
(TOL = Total Tolerance)
Calculate the low-side constraint by taking the maxi-
mum system I/O voltage, subtracting the maximum
allowable I/O to CORE difference and adding the total
system tolerance.
CORESET MIN = I/O MAX - ? V I/OC + TOL
The following comprise the sources for the total
system tolerance:
? Resistor resolution error
temperature of the MOSFET at +85°C ambient temper-
ature is:
T J = T AMB + P PULSE x Z θ JA
= +85°C + 6W x 0.05 x +70°C/W = +106°C
?
?
?
?
Resistor tolerance error
Resistor temperature drift (TCR) error
MAX5039/MAX5040 reference error
Loop-gain error
Programming the CORE Voltage
See the application circuit examples in Figures 9 and 10.
The following explains constraints on the CORE voltage.
For example:
? V CORE = 1.800 ± 5%
The high-side constraint requires that the CORE regula-
tor maintain a minimum voltage during normal opera-
tion. The low-side limit requires that the CORE regulator
hold the CORE voltage such that the voltage difference
from I/O to CORE does not exceed the processor’s
maximum allowable voltage difference:
?
?
?
V I/O = 3.300 ±5%
Maximum voltage that I/O can exceed CORE
without damage to the processor:
? V I/OC = (V I/O - V CORE ) MAX = 2V
System minimum gain = 1000V/V
______________________________________________________________________________________
15
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