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参数资料
| 型号： | MAX5040EUB+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 3/21页 |
| 文件大小： | 0K |
| 描述： | IC CNTRLR VOLT TRACK 10-UMAX |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 处理器 |
| 电流 - 电源： | 1.3mA |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-µMAX |
| 包装： | 带卷 (TR) |
Voltage-Tracking Controllers for
PowerPC, DSPs, and ASICs
ELECTRICAL CHARACTERISTICS (continued)
(V CC = 2.5V to 5.5V, V UVLO = 2V, V CORE = 1.8V, V I/O = 2.5V, V CORE_FB = 1V, V I/O_SENSE = 2V (MAX5040 only),
T A = -40°C to +85°C, unless otherwise specified. Typical values are at V CC = 5V, T A = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Regulator Amp Gain
A VOL
4000
V/V
CORE Pulldown Resistance
V CORE = 1.8V, V UVLO = 1V, V CC = 2.5V
20
50
?
MONITOR OUTPUTS
SDO Output Low Voltage
SDO Output High Voltage
V OLSDO
V OHSDO
I SDO = 1.8mA, V UVLO = 1V, V CC = 2.5V
I SDO = -1.0mA, V CC = 4V
I SDO = -1.0mA, V CC = 2.5V
V CC -
0.4V
V CC -
0.55V
0.4
V
V
I/O_SENSE Trip Threshold
V I/O_REF
V I/O_SENSE rising
Hysteresis
1.200
1.230
25
1.260
V
mV
POK Output Low Voltage
POK Leakage Current
POK Glitch Rejection Time
V OLPOK
I LPOK
t POK
I POK = 1.8mA
V POK = V CC
(Note 7)
50
0.4
1.0
V
μA
μs
Fault Time
t FAULT
(Note 8)
10
15
20
ms
I/O and CORE INPUTS
I/O Input Bias Current
CORE Input Bias Current
I/O_SENSE Input Bias Current
CORE_FB Input Bias Current
V I/O = 1V
V CORE = 1V
V I/O_SENSE = 0.8V
V CORE_FB = 1.2V
20
20
250
300
μA
μA
nA
nA
Note 1: V CC slew-rate limited to 30V/μs.
Note 2: SDO automatically goes low when the UVLO pin drops below its threshold (or V CC drops below 2.5V). SDO remains low as
V CC falls. For some V CC below V CCLO SDO may float.
Note 3: This undervoltage lockout disables the MAX5039/MAX5040 at V CC voltages below which the device cannot effectively oper-
ate. When V CC drops below the threshold, SDO goes low, the bleeder turns off, and POK is high impedance.
Note 4: In order to regulate correctly, V CC must be higher than V CORE plus the turn-on voltage of the external N-channel MOSFET.
Note 5: I/O and CORE valid mean the voltages on these pins have settled within their target specifications for normal operation.
Note 6: CORE and I/O supplies rise and fall rates must be limited to less than 6.6V/μs.
Note 7: POK does not deassert for glitches less than t POK .
Note 8: A fault condition is latched when either of the two following conditions maintains for longer than t FAULT :
V CORE_FB < V C_REF (i.e., V CORE is less than its set point)
V I/O < V CORE
A FAULT condition forces SDO and POK (MAX5040 only) low. CORE discharges to GND through 20 ? while V CC > 2.5V.
Cycle UVLO or V CC low, then high, to clear a FAULT.
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