参数资料
型号: MAX5064BATC+T
厂商: Maxim Integrated
文件页数: 11/20页
文件大小: 0K
描述: IC MOSFET DRIVER 12-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
配置: 半桥
输入类型: 差分
延迟时间: 35ns
电流 - 峰: 2A
配置数: 1
输出数: 2
高端电压 - 最大(自引导启动): 125V
电源电压: 8 V ~ 12.6 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 12-WQFN 裸露焊盘
供应商设备封装: 12-TQFN-EP(4x4)
包装: 带卷 (TR)
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
Topologies like the two-switch forward converter, where
both high- and low-side switches are turned on and off
simultaneously, can have the BBM function disabled by
leaving BBM unconnected. When disabled, t BBM is typi-
cally 1ns.
Driver Logic Inputs (IN_H, IN_L, IN_H+,
IN_H-, IN_L+, IN_L-)
The MAX5062_/MAX5064A are CMOS (V DD / 2) logic-
input drivers while the MAX5063_/MAX5064B have TTL-
compatible logic inputs. The logic-input signals are
independent of V DD . For example, the IC can be pow-
ered by a 10V supply while the logic inputs are provid-
ed from a 12V CMOS logic. Also, the logic inputs are
protected against voltage spikes up to 15V, regardless
shoot-through in the absence of external BBM delay
during the narrow pulse at low duty cycle (see Figure 2).
At high duty cycle (close to 100%) the DH minimum low
pulse width (t DMIN-DH-L ) must be higher than the DL
minimum low pulse width (t DMIN-DL-L ) to avoid overlap
and shoot-through (see Figure 3). In the case of
MAX5062/MAX5063/MAX5064, there is a possibility of
about 40ns overlap if an external BBM delay is not pro-
vided. We recommend adding external delay in the INH
path so that the minimum low pulse width seen at INH
is always longer than t PW-MIN . See the Electrical
Characteristics table for the typical values of t PW-MIN .
V DD
of the V DD voltage. The TTL and CMOS logic inputs
have 400mV and 1.6V hysteresis, respectively, to avoid
double pulsing during transition. The logic inputs are
high-impedance pins and should not be left floating.
A)
V IN
The low 2.5pF input capacitance reduces loading and
increases switching speed. The noninverting inputs are
pulled down to GND and the inverting inputs are pulled
PWM IN
INH
DH
N
V OUT
up to V DD internally using a 1M ? resistor. The PWM
HS
output from the controller must assume a proper state
while powering up the device. With the logic inputs
INL
DL
N
floating, the DH and DL outputs pull low as V DD rises
up above the UVLO threshold.
The MAX5064_ has two logic inputs per driver, which
provide greater flexibility in controlling the MOSFET.
MAX5062B/MAX5062D/MAX5063B/MAX5063D/MAX5064
Use IN_H+/IN_L+ for noninverting logic and IN_H-/
IN_L- for inverting logic operation. Connect
IN_H+/IN_L+ to V DD and IN_H-/IN_L- to GND if not
used. Alternatively, the unused input can be used as an
ON/OFF function. Use IN_+ for active-low and IN_- for
active-high shutdown logic.
Table 1. MAX5064_ Truth Table
B)
PWM IN
t DMIN-DH-H
IN_H+/IN_L+
Low
Low
High
High
IN_H-/IN_L-
Low
High
Low
High
DH/DL
Low
Low
High
Low
DH
Minimum Pulse Width
The MAX5062/MAX5063/MAX5064 uses a single-shot
level shifter architecture to achieve low propagation
delay. Typical level shifter architecture causes a mini-
mum (high or low) pulse width (t DMIN ) at the output that
may be higher than the logic-input pulse width. For
MAX5062/MAX5063/MAX5064 devices, the DH mini-
mum high pulse width (t DMIN-DH-H ) is lower than the DL
minimum low pulse width (t DMIN-DL-L ) to avoid any
BUILT-IN
DEAD TIME
DL
t DMIN-DL-L
Figure 2. Minimum Pulse-Width Behavior for Narrow Duty-
Cycle Input (On-Time < t PW-MIN )
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