参数资料
型号: MAX5064BATC+T
厂商: Maxim Integrated
文件页数: 12/20页
文件大小: 0K
描述: IC MOSFET DRIVER 12-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
配置: 半桥
输入类型: 差分
延迟时间: 35ns
电流 - 峰: 2A
配置数: 1
输出数: 2
高端电压 - 最大(自引导启动): 125V
电源电压: 8 V ~ 12.6 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 12-WQFN 裸露焊盘
供应商设备封装: 12-TQFN-EP(4x4)
包装: 带卷 (TR)
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
V DD
V IN
A)
EXTERNAL
C)
PWM IN
PWM IN
BBM DELAY
INH
DH
N
V OUT
HS
INL
DL
N
EXTERNAL
BBM DELAY
t DMIN-DH-L
DH
MAX5062B/MAX5062D/MAX5063B/MAX5063D/MAX5064
V DD
V IN
B)
POTENTIAL
EXTERNAL
OVERLAP TIME
PWM IN
BBM DELAY
INH
DH
N
V OUT
HS
DL
INL
DL
N
t DMIN-DL-H
MAX5062A/MAX5062C/MAX5063A/MAX5063C/MAX5064
Figure 3. Minimum Pulse-Width Behavior for High Duty-Cycle Input (Off-Time < t PW-MIN )
P D = ?? C L DD SW ?? + ( I DDO BSTO DD
) × V
× V
× f
+ I
Applications Information
Supply Bypassing and Grounding
Pay extra attention to bypassing and grounding the
MAX5062/MAX5063/MAX5064. Peak supply and output
currents may exceed 4A when both drivers are driving
large external capacitive loads in-phase. Supply drops
and ground shifts create forms of negative feedback for
inverters and may degrade the delay and transition
times. Ground shifts due to insufficient device ground-
ing may also disturb other circuits sharing the same AC
ground return path. Any series inductance in the V DD ,
DH, DL, and/or GND paths can cause oscillations due
to the very high di/dt when switching the MAX5062/
MAX5063/MAX5064 with any capacitive load. Place
one or more 0.1μF ceramic capacitors in parallel as
close to the device as possible to bypass V DD to GND
(MAX5062/MAX5063) or PGND (MAX5064). Use a
ground plane to minimize ground return resistance and
series inductance. Place the external MOSFET as close
as possible to the MAX5062/MAX5063/MAX5064 to fur-
ther minimize board inductance and AC path resis-
tance. For the MAX5064_ the low-power logic ground
(AGND) is separated from the high-power driver return
(PGND). Apply the logic-input signal between IN_ to
AGND and connect the load (MOSFET gate) between
DL and PGND.
Power Dissipation
Power dissipation in the MAX5062/MAX5063/MAX5064
is primarily due to power loss in the internal boost
diode and the nMOS and pMOS FETS.
For capacitive loads, the total power dissipation for the
device is:
2
12
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