参数资料
型号: MAX5064BATC+T
厂商: Maxim Integrated
文件页数: 8/20页
文件大小: 0K
描述: IC MOSFET DRIVER 12-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
配置: 半桥
输入类型: 差分
延迟时间: 35ns
电流 - 峰: 2A
配置数: 1
输出数: 2
高端电压 - 最大(自引导启动): 125V
电源电压: 8 V ~ 12.6 V
工作温度: -40°C ~ 125°C
安装类型: 表面贴装
封装/外壳: 12-WQFN 裸露焊盘
供应商设备封装: 12-TQFN-EP(4x4)
包装: 带卷 (TR)
125V/2A, High-Speed,
Half-Bridge MOSFET Drivers
MAX5062/MAX5063 Pin Description
PIN
1
2
3
4
5
6
7
8
PIN
1
2
3
4
5
6
7
8
9
10
11
12
NAME
V DD
BST
DH
HS
IN_H
IN_L
GND
DL
EP
NAME
BST
DH
HS
AGND
BBM
IN_H-
IN_H+
IN_L-
IN_L+
PGND
DL
V DD
EP
FUNCTION
Power Input. Bypass to GND with a parallel combination of 0.1μF and 1μF ceramic capacitor.
Boost Flying Capacitor Connection. Connect a 0.1μF ceramic capacitor between BST and HS for the
high-side MOSFET driver supply.
High-Side-Gate Driver Output. Driver output for the high-side MOSFET gate.
Source Connection for High-Side MOSFET. Also serves as a return terminal for the high-side driver.
High-Side Noninverting Logic Input
Low-Side Noninverting Logic Input (MAX5062A/C, MAX5063A/C). Low-side inverting logic input
(MAX5062B/D, MAX5063B/D).
Ground. Use GND as a return path to the DL driver output and IN_H/IN_L inputs.
Low-Side-Gate Driver Output. Drives low-side MOSFET gate.
Exposed Pad. Internally connected to GND. Externally connect the exposed pad to a large ground
plane to aid in heat dissipation (MAX5062C/D, MAX5063C/D only).
MAX5064 Pin Description
FUNCTION
Boost Flying Capacitor Connection. Connect a 0.1μF ceramic capacitor between BST and HS for the
high-side MOSFET driver supply.
High-Side-Gate Driver Output. Drives high-side MOSFET gate.
Source Connection for High-Side MOSFET. Also serves as a return terminal for the high-side driver.
Analog Ground. Return path for low-switching current signals. IN_H/IN_L inputs referenced to
Break-Before-Make Programming Resistor Connection. Connect a 10k ? to 100k ? resistor from BBM
to AGND to program the break-before-make time (t BBM ) from 16ns to 95ns. Resistance values
greater than 200k ? disables the BBM function and makes t BBM = 1ns. Bypass this pin with at least a
1nF capacitor to AGND.
High-Side Inverting CMOS (V DD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to
AGND when not used.
High-Side Noninverting CMOS (V DD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to
V DD when not used.
Low-Side Inverting CMOS (V DD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to AGND
when not used.
Low-Side Noninverting CMOS (V DD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to
V DD when not used.
Power Ground. Return path for high-switching current signals. Use PGND as a return path for the
low-side driver.
Low-Side-Gate Driver Output. Drives the low-side MOSFET gate.
Power Input. Bypass to PGND with a 0.1μF ceramic in parallel with a 1μF ceramic capacitor.
Exposed Pad. Internally connected to AGND. Externally connect to a large ground plane to aid in
heat dissipation.
8
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