参数资料
型号: MAX6874ETJ
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 电源管理
英文描述: EEPROM-Programmable, Hex/Quad, Power-Supply Sequencers/Supervisors
中文描述: 6-CHANNEL POWER SUPPLY MANAGEMENT CKT, QCC32
封装: 7 X 7 MM, 0.80 MM HEIGHT, MO-220, TQFN-32
文件页数: 17/40页
文件大小: 337K
代理商: MAX6874ETJ
MAX6874/MAX6875
EEPROM-Programmable, Hex/Quad,
Power-Supply Sequencers/Supervisors
24
______________________________________________________________________________________
ured by the user). To configure the MAX6874/ MAX6875,
first apply an input voltage to IN1 or one of IN3–IN5
(MAX6874)/IN3–IN4 (MAX6875) (see the Powering the
MAX6874/MAX6875 section). VIN1 > +4V or one of
VIN3–VIN5 > +2.7V, to ensure device operation. Next,
transmit data through the serial interface. Use the block
write protocol to quickly configure the device. Write to
the configuration registers first to ensure the device is
configured properly. After completing the setup proce-
dure, use the read word protocol to verify the data from
the configuration registers. Lastly, use the write word
protocol to write this data to the EEPROM registers. After
completing EEPROM register configuration, apply full
power to the system to begin normal operation. The non-
volatile EEPROM stores the latest configuration upon
removal of power. Write 0’s to all EEPROM registers to
clear the memory.
Software Reboot
A software reboot allows the user to restore the
EEPROM configuration to the volatile registers without
cycling the power supplies. Use the send byte com-
mand with data byte 88h to initiate a software reboot.
The 3.5ms (max) power-up delay also applies after a
software reboot.
SMBus/I2C-Compatible Serial Interface
The MAX6874/MAX6875 feature an I2C/SMBus-compati-
ble serial interface consisting of a serial data line (SDA)
and a serial clock line (SCL). SDA and SCL allow bidirec-
tional communication between the MAX6874/MAX6875
and the master device at clock rates up to 400kHz.
Figure 2 shows the interface timing diagram. The
MAX6874/MAX6875 are transmit/receive slave-only
devices, relying upon a master device to generate a
clock signal. The master device (typically a microcon-
troller) initiates data transfer on the bus and generates
SCL to permit that transfer.
AFFECTED OUTPUTS
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT RANGE
MAX6874
MAX6875
DESCRIPTION
11h
8011h
[3:1]
PO1
15h
8015h
[3:1]
PO2
1Ch
801Ch
[4:2]
PO3
PO1
23h
8023h
[4:2]
PO4
PO2
2Ah
802Ah
[3:1]
PO5
PO3
31h
8031h
[3:1]
PO6
PO4
35h
8035h
[3:1]
PO7
PO5
39h
8039h
[3:1]
PO8
000 = 25s
001 = 1.5625ms
010 = 6.25ms
011 = 25ms
100 = 50ms
101 = 200ms
110 = 400ms
111 = 1600ms
Table 16. PO_ Timeout Periods
REGISTER
ADDRESS
EEPROM
MEMORY
ADDRESS
BIT
RANGE
DESCRIPTION
[0]
PO1 (MAX6874 only). 0 = active low, 1 = active high.
[1]
PO2 (MAX6874 only). 0 = active low, 1 = active high.
[2]
PO3 (MAX6874)/PO1 (MAX6875). 0 = active low, 1 = active high.
[3]
PO4 (MAX6874)/PO2 (MAX6875). 0 = active low, 1 = active high.
[4]
PO5 (MAX6874)/PO3 (MAX6875). 0 = active low, 1 = active high.
[5]
PO6 (MAX6874)/PO4 (MAX6875). 0 = active low, 1 = active high.
[6]
PO7 (MAX6874)/PO5 (MAX6875). 0 = active low, 1 = active high.
3Ah
803Ah
[7]
PO8 (MAX6874 only). 0 = active low, 1 = active high.
Table 15. Programmable Output Active States
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