参数资料
型号: MAX769EEI+
厂商: Maxim Integrated Products
文件页数: 7/16页
文件大小: 0K
描述: IC PAGER SYSTEM 28-QSOP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
应用: 手持/移动设备
电流 - 电源: 4µA
电源电压: 1.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-QSOP
供应商设备封装: 28-QSOP
包装: 管件
2 or 3-Cell, Step-Up/Down,
Two-Way Pager System IC
Pin Description
PIN
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
NAME
LX1
SDI
SDO
PGND
SCL
LBO
RSO
REF
CH0
RSIN
LBI
FILT
SYNC
OFS
AGND
DRGND
DR1
DR2IN
DR2
REG3
REG2
R2IN
NICD
REG1
OUT
BATT
CS
LX2
FUNCTION
Connect LX1 to the inductor. LX1 is internally connected to an NFET that switches to PGND and a PFET that
switches to OUT.
Serial Data Input for SPI Interface
Serial Data Output for SPI Interface
Power Ground. Source of LX1 and LX2 NFETs.
Serial Clock for SPI Interface
Open-Drain Output for LBI Comparator
Reset Output. Open drain goes low when RSIN drops below 0.6V. All serial registers are reset (or set) to
POR state as well.
1.28V Reference. Bypass with a 1μF capacitor.
CH0 is compared to a 7-bit DAC that adjusts from 0.2V to 1.27V. The comparison result is sent to the CH0
OUT register.
Reset Input. Triggers RSO and resets IC when input is below 0.6V. Comparator with hysteresis (18mV).
Low-Battery Input. Triggers LBO and internal serial bit.
An external RC network sets the PLL loop response to adjust frequency lock time versus jitter: 1nF || (22nF +
10k ? ).
Sync Input for PWM Switch Rate. A 38.4kHz input results in a 268.8kHz PWM rate (seven times the SYNC
frequency).
Resistor sets offset between OUT (or REG1 or any other point) and REG2. R OFS = 15k ? results in 150mV.
Analog Ground
Ground for DR1 and DR2 FET Sources
Open-Drain FET Switch. Activated via the serial-interface bit.
Logic Input. ANDed with the DR2ON bit to control the DR2 switch.
Open-Drain FET Switch. On via AND of the DR2ON bit and the DR2IN pin.
1V, 2mA Regulator Output. On via the serial interface. Low noise.
24mA REG2 Output. Linearly regulated to the voltage at the OFS pin (voltage difference = 10μA x R OFS ).
REG2 isolates noise.
REG2 Input. Connect to OUT, REG1, or another voltage source.
15mA or 1mA Settable Charge Current from OUT to 3-Cell NiCd Stack. When the NICD_REG_ON bit is set
(Table 1), NICD becomes an input to the linear regulator at OUT, and the DC-DC converter is off.
PFET Output Connected to OUT. Output is clamped such that it cannot rise above 3.3V, regardless of the
voltage set at OUT.
DC-DC Converter Output and Feedback Point. Digitally controlled from 1.8V to 4.9V in 100mV steps
(Table 5).
Positive Connection to Battery. The IC is powered from OUT.
Chip Select for SPI Serial Interface
Connect LX2 to the other inductor terminal. LX2 is internally connected to an NFET that switches to PGND
and a PFET that switches to BATT.
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