参数资料
型号: MAX8702ETP+T
厂商: Maxim Integrated
文件页数: 6/14页
文件大小: 0K
描述: IC DRVR MOSFET DUAL 20-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
配置: 高端和低端,同步
输入类型: PWM
延迟时间: 25ns
电流 - 峰: 1.5A
配置数: 4
输出数: 4
电源电压: 4.5 V ~ 28 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 20-WFQFN 裸露焊盘
供应商设备封装: 20-TQFN-EP(4x4)
包装: 带卷 (TR)
Dual-Phase MOSFET Drivers
with Temperature Sensor
Pin Description
PIN
MAX8702 MAX8703
NAME
FUNCTION
1
2
3
1
2
3
PWM1
PWM2
AGND
Phase 1 PWM Logic Input. DH1 is high when PWM1 is high; DL1 is high when PWM1 is low.
Phase 2 PWM Logic Input. DH2 is high when PWM2 is high; DL2 is high when PWM2 is low.
Analog Ground. The AGND and PGND_ pins must be connected externally at one point close to
the IC. Connect the device ’ s exposed backside pad to AGND.
Temperature-Set Input. Connect an external 1% resistor from TSET to AGND to set the trip point.
4
TSET
R TSET = 85,210 / T - 745,200 / T 2 - 195, where R TSET is the temperature-setting resistor in k ?
and T is the trip temperature in Kelvin.
5
6
DRHOT
I.C.
Driver-Hot-Indicator Output. DRHOT is an open-drain output. Pull up with an external resistor.
When the device ’ s temperature exceeds the programmed set point, DRHOT is pulled low.
Internally Connected. Connect to AGND.
Internal Control Circuitry Supply Input. The input voltage range is from 4.5V to 5.5V. Bypass V CC
7
7
V CC
to AGND with a 1μF ceramic capacitor. The maximum resistance between V CC and V DD should
be 10 ? .
8
9
10
8
9
10
BST2
DH2
LX2
Phase 2 Bootstrap Flying-Capacitor Connection. An optional resistor in series with BST2 allows
the DH2 pullup current to be adjusted.
Phase 2 High-Side Gate-Driver Output. DH2 swings between LX2 and BST2.
Phase 2 Inductor Switching Node Connection. LX2 is the internal lower supply rail for the DH2
high-side gate driver. LX2 is also the input to the skip-mode zero-crossing comparator.
11
11
PGND2 Phase 2 Power Ground. PGND2 is the internal lower supply rail for the DL2 low-side gate driver.
12
13
14
12
13
14
DL2
V DD
DL1
Phase 2 Low-Side Gate-Driver Output. DL2 swings between PGND2 and V DD . DL2 is high in
shutdown.
DL_ Gate-Driver Supply Input. The input voltage range is from 4.5V to 5.5V. Bypass V DD to the
power ground with a 2.2μF ceramic capacitor.
Phase 1 Low-Side Gate-Driver Output. DL1 swings between PGND1 and V DD . DL1 is high in
shutdown.
15
15
PGND1 Phase 1 Power Ground. PGND1 is the internal lower supply rail for the DL1 low-side gate driver.
16
17
18
16
17
18
LX1
DH1
BST1
Phase 1 Inductor Switching Node Connection. LX1 is the internal lower supply rail for the DH1
high-side gate driver. LX1 is also the input to the skip-mode zero-crossing comparator.
Phase 1 High-Side Gate-Driver Output. DH1 swings between LX1 and BST1.
Phase 1 Bootstrap Flying-Capacitor Connection. An optional resistor in series with BST1 allows
the DH1 pullup current to be adjusted.
Pulse-Skipping-Mode Control Input. The pulse-skipping mode is enabled when SKIP is low.
19
19
SKIP
When SKIP is high, both drivers operate in PWM mode (i.e., except during dead times, DL_ is the
complement of DH_).
20
20
4, 5, 6
SHDN
N. C.
Shutdown Control Input. When SHDN and SKIP are low, DH_ is forced low, DL_ forced high, and
the device enters into a low-power shutdown state. Temperature sensing is disabled in shutdown.
No Connection. Not internally connected.
6
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