参数资料
型号: MAX8702ETP+T
厂商: Maxim Integrated
文件页数: 9/14页
文件大小: 0K
描述: IC DRVR MOSFET DUAL 20-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
配置: 高端和低端,同步
输入类型: PWM
延迟时间: 25ns
电流 - 峰: 1.5A
配置数: 4
输出数: 4
电源电压: 4.5 V ~ 28 V
工作温度: -40°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 20-WFQFN 裸露焊盘
供应商设备封装: 20-TQFN-EP(4x4)
包装: 带卷 (TR)
Dual-Phase MOSFET Drivers
with Temperature Sensor
(2) IRF7811W n-channel MOSFETs are used on the
high side. According to the manufacturer ’ s data sheet,
a single IRF7811W has a maximum gate charge of 24nC
(V GS = 5V). Using the above equation, the required
boost capacitance is:
system power is removed without going through the
proper shutdown sequence.
Low-Power Pulse Skipping
The MAX8702/MAX8703 enter into low-power pulse-
skipping mode when SKIP is pulled low. In skip mode,
C BST =
2 x 24nC
200 mV
= 0 . 24 μ F
an inherent automatic switchover to pulse frequency
modulation (PFM) takes place at light loads. A zero-
crossing comparator truncates the low-side switch on-
Selecting the closest standard value, this example
requires a 0.22μF ceramic capacitor.
5V Bias Supply (V CC and V DD )
V DD provides the supply voltages for the low-side dri-
vers (DL). The decoupling capacitor at V DD also
charges the BST capacitors during the time period
when DL is high. Therefore, the V DD capacitor should
be large enough to minimize the ripple voltage during
switching transitions. C VDD should be chosen accord-
ing to the following equation:
C VDD = 10 x C BST
In the example above, a 0.22μF capacitor is used for
C BST , so the V DD capacitor should be 2.2μF.
V CC provides the supply voltage for the internal logic
circuit and temperature sensor. To avoid switching
noise from coupling into the sensitive internal circuit, an
RC filter is recommended for the V CC pin. Place a 10 ?
resistor from the supply voltage to the V CC pin and a
1μF capacitor from the V CC pin to AGND.
The total bias current I BIAS from the 5V supply can be
calculated using the following equation:
I BIAS = I DD + I CC
I DD = n PHASE x f SW x (n NH x Q G(NH) + n NL x Q G(NL) )
where n PHASE is the number of phases, f SW is the
switching frequency, Q G(NH) and Q G(NL) are the
MOSFET data sheet ’ s total gate-charge specification
limits at V GS = 5V, n NH is the total number of high-side
MOSFETs in parallel, n NL is the total number of low-
side MOSFETs in parallel, and I CC is the V CC supply
current.
Undervoltage Lockout (UVLO)
When V CC is below the UVLO threshold (3.85V typ) and
SHDN and SKIP are low, DL is kept high and DH is
time at the inductor current ’ s zero-crossing. The
comparator senses the voltage across LX and PGND.
Once V LX - V PGND drops below the zero-crossing com-
parator threshold (see the Electrical Characteristics ),
the comparator forces DL low. This mechanism causes
the threshold between pulse-skipping PFM and non-
skipping PWM operation to coincide with the boundary
between continuous and discontinuous inductor-cur-
rent operation. The PFM/PWM crossover occurs when
the load current of each phase is equal to 1/2 the peak-
to-peak ripple current, which is a function of the induc-
tor value. For a battery input range of 7V to 20V, this
threshold is relatively constant, with only a minor
dependence on the input voltage due to the typically
low duty cycles. The switching waveforms may appear
noisy and asynchronous when light loading activates
the pulse-skipping operation, but this is a normal oper-
ating condition that results in high light-load efficiency.
Shutdown
The MAX8702/MAX8703 feature a low-power shutdown
mode that reduces the V CC quiescent current drawn to
2μA (typ). Driving SHDN and SKIP low sets DH low and
DL high. Temperature sensing is disabled in shutdown.
Temperature Sensor (MAX8702 Only)
The MAX8702 includes a fully integrated resistor-pro-
grammable temperature sensor. The sensor incorpo-
rates two temperature-dependent reference signals
and one comparator. One signal exhibits a characteris-
tic that is proportional to temperature, and the other is
complementary to temperature. The temperature at
which the two signals are equal determines the thermal
trip point. When the temperature of the device exceeds
the trip point, the open-drain output DRHOT pulls low.
Table 3. Modes of Operation
held low. This provides output overvoltage protection
as soon as the supply voltage is applied. Once V CC is
above the UVLO threshold and SHDN is high, DL and
DH levels depend on the PWM signal applied. If V CC
falls below the UVLO threshold while SHDN is high,
both DL and DH are immediately forced low. This pre-
vents negative undershoots on the output when the
SHDN
L
L
H
H
SKIP
L
H
L
H
MODE OF OPERATION
Low-power shutdown state;
temperature sensing disabled
PWM operation
Pulse-skipping operation
PWM operation
_______________________________________________________________________________________
9
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