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| 型号： | MAX8707ETL+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 16/37页 |
| 文件大小： | 0K |
| 描述： | IC CNTRLR MULTIPHASE 40TQFN |
| 标准包装： | 2,500 |
| 应用： | 控制器，AMD Hammer CPU 电源 |
| 输入电压： | 4.5 ~ 5.5 V |
| 输出数： | 4 |
| 输出电压： | 0.8 ~ 1.55 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-WFQFN 裸露焊盘 |
| 供应商设备封装： | 40-TQFN-EP（6x6） |
| 包装： | 带卷 (TR) |
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Multiphase, Fixed-Frequency Controller for
AMD Hammer CPU Core Power Supplies
Pin Description (continued)
PIN
30
31
32
33
34
35
36
37
38
39
40
NAME
CRSP
CSP1
CSN1
CSN2
CSP2
CSP3
CSN3
CSN4
CSP4
D0
D1
FUNCTION
Positive Current-Sense Resistor Input. CRSP is the positive differential input used for accurate sensing of
the phase 1 inductor current. Connect a current-sense resistor between CRSP and CRSN. If current-sense
resistors are used on all phases (CSP_, CSN_), this additional current-sense (CRSP, CRSN) feature can be
disabled by connecting CRSP to V CC and floating CRSN.
Positive Current-Sense Input for Phase 1. This input should be connected to the positive terminal of the
current-sense resistor or of the DCR sensing filtering capacitor, depending on the current-sense method
implemented.
Negative Current-Sense Input for Phase 1
Negative Current-Sense Input for Phase 2
Positive Current-Sense Input for Phase 2. This input should be connected to the positive terminal of the
current-sense resistor or of the DCR sensing filtering capacitor, depending on the current-sense method
implemented.
Positive Current-Sense Input for Phase 3. This input should be connected to the positive terminal of the
current-sense resistor or of the DCR sensing filtering capacitor, depending on the current-sense method
implemented.
Negative Current-Sense Input for Phase 3
Negative Current-Sense Input for Phase 4
Positive Current-Sense Input for Phase 4. This input should be connected to the positive terminal of the
current-sense resistor or of the DCR sensing filtering capacitor, depending on the current-sense method
implemented. Connect CSP4 to V CC for fixed 3-phase operation.
Low-Voltage VID-DAC Code Inputs. The D0 – D4 inputs do not have internal pullups. These 1.0V logic
inputs are designed to interface directly with the CPU. In normal mode (Table 4, SUS = low), the output
voltage is set by the D0 – D4 VID-DAC inputs. In suspend mode (SUS = high), the output voltage tracks the
voltage at SUSV.
Low-Voltage VID-DAC Code Inputs
Detailed Description
+5V Bias Supply (V CC )
The MAX8707 requires an external +5V bias supply in
addition to the battery. Typically, this +5V bias supply is
the notebook ’ s 95%-efficient, +5V system supply.
Keeping the bias supply external to the controller
improves efficiency and eliminates the cost associated
with the +5V linear regulator that would otherwise be
needed to supply the PWM circuit and gate drivers. If
stand-alone capability is needed, the +5V bias supply
can be generated with an external linear regulator.
The +5V bias supply must provide V CC (PWM con-
troller) and V DRV (FET gate-drive power), so the maxi-
mum current drawn is:
I BIAS = I CC + I DRIVE
where I CC is provided in the Electrical Characteristics
table and I DRIVE is the driver ’ s supply current dominat-
ed by f SW x Q G (per phase) as defined in the driver ’ s
data sheet. If the +5V bias supply is powered up prior
to the battery supply, the enable signal ( SHDN going
from low to high) must be delayed until the battery volt-
age is present to ensure startup.
16
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