参数资料
| 型号： | MAX8756ETI+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 18/30页 |
| 文件大小： | 0K |
| 描述： | IC CNTRL DUAL PS 28-TQFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 应用： | 控制器，笔记本电脑电源系统 |
| 输入电压： | 4 V ~ 26 V |
| 输出数： | 2 |
| 输出电压： | 1.5V，1.8V，1 V ~ 2.3 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-WFQFN 裸露焊盘 |
| 供应商设备封装： | 28-TQFN-EP（4x4） |
| 包装： | 带卷 (TR) |
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Interleaved High-Efficiency, Dual Power-Supply
Controllers for Notebook Computers
V OUT ( PWM ) = V NOM ? 1 ?
? ? ? ?
A SLOPE ( V IN ? V NOM ) ? ? V RIPPLE ?
?
?
Output Voltage
DC output accuracy specifications in the Electrical
Characteristics refer to the error comparator’s thresh-
old. When the inductor continuously conducts, the
?
?
V IN 2
?
MAX8716/MAX8717/MAX8756/MAX8757 regulate the
peak of the output ripple, so the actual DC output volt-
age is lower than the slope-compensated trip level by
50% of the output ripple voltage. For PWM operation
(continuous conduction), the output voltage is accu-
rately defined by the following equation:
Table 4. SKIP_ Configuration Table
where V NOM is the nominal output voltage, A SLOPE
equals 1%, and V RIPPLE is the output ripple voltage
(V RIPPLE = R ESR x Δ I INDUCTOR as described in the
Output Capacitor Selection section).
In discontinuous conduction (I OUT < I LOAD(SKIP) ), the
MAX8716/MAX8717/MAX8756/MAX8757 regulate the
valley of the output ripple, so the output voltage has a DC
regulation level higher than the error-comparator thresh-
1 ? ? SW ?
2 ? ? ? OSC ? ?
SKIP_
V CC
GND
REF
MODE
Forced-PWM
mode
Skip mode
Low-noise
skip mode
COMMENTS
Fixed-frequency operation.
Constant output ripple voltage.
Able to source and sink current.
High efficiency at light loads.
Source-only applications.
Good efficiency at light loads.
(V IDLE / V LN ) times smaller no-load
ripple and (V IDLE / V LN ) 2 times higher
frequency compared with skip mode.
Source-only applications.
old. For PFM operation (discontinuous conduction), the
output voltage is approximately defined by the following
equation:
V OUT ( PFM ) = V NOM + I IDLE R ESR
where V NOM is the nominal output voltage, f OSC is the
maximum switching frequency set by the internal oscil-
lator, f SW is the actual switching frequency, and I IDLE is
the Idle Mode inductor current when pulse skipping.
Table 5. Operating Modes Truth Table
MODE
Power-Up
Run
Output Overvoltage
Protection (OVP)
MAX8716/MAX8717/
MAX8756 Only
Output Undervoltage
Protection (UVP)
Shutdown
Thermal Shutdown
CONDITION
V CC UVLO
ON1 or ON2 enabled
Either output > 115% of nominal level
Either output < 70% of nominal level,
UVP is enabled 6144 clock cycles
(1/f OSC ) after the output is enabled
(ON_ going high)
ON1 and ON2 are driven low
T J > +160°C
COMMENT
DL_ tracks V CC as V CC rises from 0V to +5V.
When ON_ is low, DL_ tracks V CC as V CC falls.
When ON_ is high, DL_ is forced low as V CC falls below the
3.95V (typ) falling UVLO threshold. DL_ is forced high when
V CC falls below 1V (typ).
Normal operation.
When the overvoltage (OV) comparator trips, the faulted side
sets the OV latch, forcing PGOOD_ low and DL_ high. The
other controller is not affected.
The OV latch is cleared by cycling V CC below 1V or cycling
the respective ON_ pin.
When the undervoltage (UV) comparator trips, the faulted
side sets the UV latch, forcing PGOOD_ low and initiating the
soft-shutdown sequence by pulsing only DL_. DL_ goes high
after soft-shutdown. The other controller is not affected.
The UV latch is cleared by cycling V CC below 1V or cycling
the respective ON_ pin.
DL_ stays high after soft-shutdown is completed.
All circuitry is shut down.
Exited by POR or cycling ON1 and ON2.
DL1 and DL2 remain high.
18
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