参数资料
型号: MAX8760ETL+
厂商: Maxim Integrated Products
文件页数: 15/39页
文件大小: 0K
描述: IC CNTRLR QUICK PWM 40-TQFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 50
系列: Quick-PWM™
应用: 控制器,6 位 VID AMD 移动式 Turion?
输入电压: 4 V ~ 28 V
输出数: 2
输出电压: 0.38 V ~ 1.55 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 40-WFQFN 裸露焊盘
供应商设备封装: 40-TQFN-EP(6x6)
包装: 管件
Dual-Phase, Quick-PWM Controller for AMD
Mobile Turion 64 CPU Core Power Supplies
Pin Description (continued)
PIN
14
15
16
17
18
19–24
25
26
27
28
29
30
31
NAME
CCI
FB
OAIN-
OAIN+
SKIP
D5–D0
VROK
BSTM
LXM
DHM
DLM
V DD
PGND
FUNCTION
Current Balance Compensation. Connect a 470pF capacitor between CCI and FB. See the Current
Balance Compensation section.
Feedback Input. FB is internally connected to both the feedback input and the output of the voltage-
positioning op amp. See the Setting Voltage Positioning section to set the voltage-positioning gain.
Op Amp Inverting Input and Op Amp Disable Input. When using the internal op amp for additional
voltage-positioning gain, connect to the negative terminal of current-sense resistor through a resistor as
described in the Setting Voltage Positioning section. Connect OAIN- to V CC to disable the op amp. The
logic threshold to disable the op amp is approximately V CC - 1V.
Op Amp Noninverting Input. When using the internal op amp for additional voltage-positioning gain,
connect to the positive terminal of current-sense resistor through a resistor as described in the Setting
Voltage Positioning section.
Pulse-Skipping Select Input. When pulse skipping, the controller blanks the VROK upper threshold:
3.3V or V CC (high) = Dual-phase forced-PWM operation
REF = Dual-phase pulse-skipping operation
GND = Single-phase pulse-skipping operation
Low-Voltage VID DAC Code Inputs. The D0–D5 inputs do not have internal pullups. These 1.0V logic
inputs are designed to interface directly with the CPU. In normal mode (Table 4, SUS = GND), the output
voltage is set by the VID code indicated by the logic-level voltages on D0–D5. In suspend mode (Table
5, SUS = REF or high), the decoded state of the four-level S0, S1 inputs sets the output voltage.
Open-Drain Power-Good Output. After output voltage transitions, except during power-up and power-
down, if OUT is in regulation then VROK is high impedance. The controller blanks VROK whenever the
slew-rate control is active (output voltage transitions). VROK is forced low in shutdown. A pullup resistor
on VROK causes additional finite shutdown current. During power-up, VROK includes a 3ms (min) delay
after the output reaches the regulation voltage.
Main Boost Flying Capacitor Connection. An optional resistor in series with BSTM allows the DHM pullup
current to be adjusted.
Main Inductor Connection. LXM is the internal lower supply rail for the DHM high-side gate driver.
Main High-Side Gate-Driver Output. Swings LXM to BSTM.
Main Low-Side Gate-Driver Output. DLM swings from PGND to V DD . DLM is forced high after the MAX8760
powers down.
Supply Voltage Input for the DLM and DLS Gate Drivers. Connect to the system supply voltage (4.5V to
5.5V). Bypass V DD to PGND with a 2.2μF or greater ceramic capacitor as close to the IC as possible.
Power Ground. Ground connection for low-side gate drivers DLM and DLS.
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