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参数资料
| 型号： | MAX8952EWE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 10/31页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 2.5A 16WLP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.77 V ~ 1.4 V |
| 输入电压： | 2.5 V ~ 5.5 V |
| 频率 - 开关： | 3.25MHz |
| 电流 - 输出： | 2.5A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-UFBGA，WLCSP |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-WLP（2x2） |
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MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Bump Description
10
PIN
A1
A2
A3
A4
B1
B2
B3, B4
C1
C2
C3, C4
D1
D2
D3
D4
NAME
IN1
AGND
VID1
IN2
SNS+
EN
LX
SNS-
VID0
PGND
V DD
SDA
SCL
SYNC
FUNCTION
Analog Supply Voltage Input. The input voltage range is 2.5V to 5.5V. Install an 11 ? resistor between
IN1 and the input supply. Bypass the IN1 to AGND with a 0.1μF ceramic capacitor as close as
possible to the IC. Connect IN1 and IN2 to the same power source.
Analog Ground. Connect AGND to the PCB ground plane.
Voltage ID Control Input. The logic states of VID0 and VID1 select the register that sets the output
voltage.
Power-Supply Voltage Input. The input voltage range is from 2.5V to 5.5V. IN2 powers the internal
p-channel and n-channel MOSFETs. Bypass IN2 to PGND with 2x 10μF and 0.1μF ceramic
capacitor as close as possible to the IC. Connect IN1 and IN2 to the same power source.
Output Voltage Remote Sense, Positive Input. Connect SNS+ directly to the output at the load.
Logic Enable Input. Drive EN high to enable the DC-DC step-down regulator, or low to place in
shutdown mode. In shutdown mode, this logic input has an internal pulldown resistor to AGND.
Inductor Connection. LX is connected to the drains of the internal p-channel and n-channel
MOSFETs. LX is high impedance during shutdown.
Output Voltage Sense, Negative Input. Connect to a quiet ground directly at the IC.
Voltage ID Control Input. The logic states of VID0 and VID1 select the register that sets the output
voltage.
Power Ground. Connect both PGND bumps to the PCB ground plane.
Logic Input Supply Voltage. Connect V DD to the logic supply driving SDA, SCL, and SYNC. Bypass
V DD to AGND with a 0.1μF ceramic capacitor. When V DD drops below the UVLO threshold, the I 2 C
registers are reset, but the EN control is still active in this mode.
I 2 C Data Input. Data is read on the rising edge of SCL and data is clocked out on the falling edge of SCL.
I 2 C Clock Input
External Clock Synchronization Input. Connect SYNC to a 13MHz, 19.2MHz, or 26MHz system clock.
The DC-DC regulator can be forced to synchronize to this external clock depending on I 2 C setting. See
Table 8. SYNC does not have an internal pulldown. Connect SYNC to AGND if not used.
Maxim Integrated
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