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参数资料
| 型号： | MAX8952EWE+T |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 30/31页 |
| 文件大小： | 0K |
| 描述： | IC REG BUCK SYNC ADJ 2.5A 16WLP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 类型： | 降压（降压） |
| 输出类型： | 可调式 |
| 输出数： | 1 |
| 输出电压： | 0.77 V ~ 1.4 V |
| 输入电压： | 2.5 V ~ 5.5 V |
| 频率 - 开关： | 3.25MHz |
| 电流 - 输出： | 2.5A |
| 同步整流器： | 是 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-UFBGA，WLCSP |
| 包装： | 带卷 (TR) |
| 供应商设备封装： | 16-WLP（2x2） |
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MAX8952
2.5A Step-Down Regulator
with Remote Sense in 2mm x 2mm WLP
Input Capacitor Selection
The input capacitor in a step-down DC-DC regulator
reduces current peaks drawn from the battery or other
input power source and reduces switching noise in the
controller. 10μF ceramic capacitors in parallel with a
0.1μF ceramic capacitor are recommended for most
applications. The impedance of the input capacitor at the
switching frequency should be less than that of the input
source so that high-frequency switching currents do not
pass through the input source. The input capacitor must
meet the input ripple-current requirement imposed by
the step-down regulator. Ceramic capacitors are pre-
ferred due to their resilience to power-up surge currents.
Choose the input capacitor so that the temperature rise
due to input ripple current does not exceed approxi-
mately +10°C. For a step-down DC-DC regulator, the
maximum input ripple current is 1/2 of the output current.
This maximum input ripple current occurs when the step-
down regulator operates at 50% duty factor (V IN = 2 x
V OUT ). Refer to the MAX8952 Evaluation Kit for specific
input capacitor recommendations.
Output Capacitor Selection
The step-down DC-DC regulator output capacitor keeps
output ripple small and ensures control-loop
stability. A 10μF ceramic capacitor in parallel with a
0.1μF ceramic capacitor is recommended for most appli-
cations. The output capacitor must also have low imped-
ance at the switching frequency. Ceramic, polymer, and
tantalum capacitors are suitable, with ceramic exhibiting
the lowest ESR and lowest high-frequency impedance.
Output ripple due to capacitance (neglecting ESR) is
approximately:
Power Dissipation
The IC has a thermal-shutdown feature that protects the
IC from damage when the die temperature exceeds
+160°C. See the Thermal-Overload Protection section
for more information. To prevent thermal overload and
allow the maximum load current on each regulator, it is
important to ensure that the heat generated by the IC
can be dissipated into the PCB.
When properly mounted on a multilayer PCB, the junc-
tion-to-ambient thermal resistance ( θ JA ) is typically
49°C/W.
PCB Layout
Due to fast switching waveforms and high current
paths, careful PCB layout is required to achieve optimal
performance. Minimize trace lengths between the IC
and the inductor, the input capacitor, and the output
capacitor; keep these traces short, direct, and wide.
The ground connections of C IN and C OUT should be as
close together as possible and connected to PGND.
Connect AGND and PGND directly to the ground plane.
The MAX8952 Evaluation Kit illustrates an example PCB
layout and routing scheme.
Special care should be taken when routing the remote
sense signals. Use a wide SNS+ trace to minimize par-
asitic inductance in the SNS+ feedback trace. Do not
use vias on the SNS+ trace because these introduce
additional inductance. Connect SNS- to the local AGND
plane for the MAX8952.
Chip Information
PROCESS: BiCMOS
V RIPPLE =
I L ( PEAK )
2 π × f OSC × C OUT
Additional ripple due to capacitor ESR is:
V RIPPLE ( ESR ) = I L ( PEAK ) × ESR
Refer to the MAX8952 Evaluation Kit for specific output
Package Information
For the latest package outline information and land patterns (foot-
prints), go to www.maximintegrated.com/packages . Note that a
“+”, “#”, or “-” in the package code indicates RoHS status only.
Package drawings may show a different suffix character, but the
drawing pertains to the package regardless of RoHS status.
capacitor recommendations.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
Refer to
16 WLP
W162B2+1
30
Maxim Integrated
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