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CHAPTER 10 EXTERNAL INTERRUPT CIRCUIT 2 (LEVEL)
10.4 External Interrupt Circuit 2 Interrupt
The external interrupt circuit 2 interrupt trigger event is the detection of a "L" level at
the external interrupt pin.
s Interrupts for External Interrupt Circuit 2 Operation
If a "L" is detected at an enabled external interrupt pin, the external interrupt request flag bit
(EIF2: IF20) is set to "1", and an interrupt request (IRQ4) to the CPU is generated. Write "0" to
the IF20 bit in the interrupt processing routine to clear the interrupt request.
Once the external interrupt request flag bit (IF20) is set to "1", IRQ4 continues to be asserted as
long as the flag set. Disabling the interrupt input by writing the IE bit (IE20 to IE27) of the EIE2
register to "0" will not clear the interrupt request. Always clear the IF20 bit.
Also, if the external interrupt pin stays "L", writing "0" to the IF20 bit without disabling the
external interrupt input will not clear the interrupt either, because IF20 will immediately be set
again by the "L" pin. After an interrupt request is generated, then, either the input must be
disabled, or the external IRQ signal de-asserted.
Check:
When enabling interrupts of CPU after wake-up from a reset, clear the IF20 bit in advance.
Note:
Wake-up from stop mode by an interrupt is possible using only the external interrupt circuit 1
and 2.
s Register and Vector Table for External Interrupt Circuit 2 Interrupts
Reference:
See Section 3.4.2 "Interrupt Processing" for details on the interrupts operation.
Table 10.4-1 Registers and Vector Table for External Interrupt Circuit 2 Interrupts
Interrupt
Interrupt level setting register
Vector table address
Register
Setting bits
Upper
Lower
IRQ4
ILR2 (007DH)
L41 (Bit 1)
L40 (Bit 0)
FFF2H
FFF3H