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CHAPTER 14 LCD CONTROLLER/DRIVER
14.3.3 Display RAM
Display RAM consists of 14 × 4-bit (7 bytes) of display data memory used to generate
the segment output signals.
s Display RAM and Output Pins
The contents of display RAM are automatically read out and output via the segment outputs in
sync with the selected common signal timing. A "1" bit is converted to a "select" (display on)
voltage and a "0" to a "deselect" (display off) voltage. Since the operation of the LCD is not
directly related to the operation of the CPU, display RAM read/write timing can be set by the
user. The SEG8 to SEG23 pins that are not made dedicated segment outputs by mask option
selection may be used as general-purpose output-only port pins, and the RAM that goes with
those pins may be used as regular RAM. (See Table 14.3-3 "Segment Outputs, Display RAM
Locations, and Sharing Port Pins".)
Table 14.3-4 "Common Outputs and Display RAM Bits Used in Each Duty Ratio Mode" shows
the relationship between duty ratio mode, common outputs, and display RAM.
Figure 14.3-7 "Segment/Common Output Pins and Corresponding Display RAM" shows which
display RAM bits are associated with each segment and common output pin.
Figure 14.3-7 Segment/Common Output Pins and Corresponding Display RAM
Address
0060H
bit3
bit2
bit1
bit0
SEG0
bit7
bit6
bit5
bit4
SEG1
0061H
bit3
bit2
bit1
bit0
SEG2
bit7
bit6
bit5
bit4
SEG3
0062H
bit3
bit2
bit1
bit0
SEG4
bit7
bit6
bit5
bit4
SEG5
0063H
bit3
bit2
bit1
bit0
SEG6
bit7
bit6
bit5
bit4
SEG7
0064H
bit3
bit2
bit1
bit0
SEG8
bit7
bit6
bit5
bit4
SEG9
0065H
bit3
bit2
bit1
bit0
SEG10
bit7
bit6
bit5
bit4
SEG11
0066H
bit3
bit2
bit1
bit0
SEG12
bit7
bit6
bit5
bit4
SEG13
COM3 COM2 COM1 COM0
Pins SEG8 to SEG13 share pins with Port 6
(P60 to P65).
Pins SEG0 to SEG7 share pins with Port 4
(P40 to P47).
RAM area and common pins used in 1/2 duty ratio mode
RAM area and common pins used in 1/3 duty ratio mode
RAM area and common pins used in 1/4 duty ratio mode