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4.6 Port 5
4.6.2
Operation of Port 5
This section describes the operations of the port 5.
s Operation of Port 5
r Operation as an output port
Writing data to the PDR5 register stores the data in the output latch. When the output latch
value is "0", the output transistor turns "ON" and an "L" level is output from the pin. When the
output latch value is "1", the transistor turns "OFF" and the pin goes to the high-impedance
state. If a pull-up is provided the output pin the pin goes to the pull-up state when the output
latch value is "1".
Reading the PDR5 register always returns the output latch value.
r Operation as an analog input
Set the PDR5 bit that corresponds to the analog input pin to "1" to turn the output transistor
"OFF".
Reading the PDR5 register always returns the output latch value.
r Operation at reset
Resetting the CPU initializes the PDR5 register value to "1". This turns all the output transistors
"OFF" and sets the pins to the high-impedance state.
r Operation in stop and watch modes
The output transistors are forcibly turned "OFF" and the pins go to the high-impedance state if
the pin state specification bit in the standby control register (STBC: SPL) is "1" when the device
changes to stop or watch mode.
Table 4.6-4 "Port-5 Pin State" lists the port-5 pin states.
SPL: Pin state specification bit in the standby control register (STBC)
Hi-z: High impedance
Note:
Pins with a pull-up resistor go to the "H" level (pull-up state) rather than to the high-
impedance state when the output transistor is turned "OFF".
Table 4.6-4 Port-5 Pin State
Pin name
Normal operation
main-sleep mode
main-stop mode (SPL=0)
sub-sleep mode
sub-stop mode (SPL=0)
watch mode (SPL=0)
Main-stop mode (SPL = 1)
sub-stop mode (SPL = 1)
watch mode (SPL = 1)
Reset
P50/AN0 to
P53/AN3
Output-only ports/analog input
Hi-z