
MB91460P Series
DS07-16615-2E
97
7.
Data Flash parallel programming mode
Note: The currently available parallel flash programmers do not support the programming of the data flash. The
programmers may be updated on request. This chapter is for information only.
7.1.
Flash configuration in parallel Flash programming mode
Parallel Flash programming mode (MD[2:0] = 111):
MB91F467PA
Note: The address in parallel programming mode is listed here without 10:0000h offset.
Set the offset by keeping FA[22:20] = 001 the same kind as used for programming of the main flash
.
Note: The “Dummy addresses for auto algorithm” are accepted although they are located below the physical
addresses of the flash macro. This address space is needed to apply correct addresses in auto algorithms.
7.2.
Address mapping from CPU to parallel programming mode
The following tables show the calculation from CPU addresses to data flash macro addresses which are used
in parallel programming.
7.2.1.
Address mapping MB91F467PA
Note: FA result is without 10:0000h offset for parallel Flash programming .
Set the offset by keeping FA[22:20] = 001 the same kind as used for programming of the main flash
.
CPU Address
(addr)
Condition
Flash
sectors
FA (flash address) Calculation
FFFB:FF00h
to
FFFC:FFFFh
-
SAS, SA0, SA1, SA2, SA3
(256 Byte + 64 Kbyte)
FA := addr - 0B:0000h
FFFC 0000H
FFFD 0000H
External bus area
FFFF FFFFH
0050 0000H
FFFB FF00H
FFFC C000H
FFFC 4000H
FFFC 8000H
External bus area
Data Flash Security Sector (256 Byte)
Data Flash Sector 3 (16 KB)
Data Flash Sector 2 (16 KB)
Data Flash Sector 1 (16 KB)
Data Flash Sector 0 (16 KB)
01 0000H
01 FFFFH
00 FF00H
01 C000H
01 4000H
01 8000H
CPU
address
Parallel
programming
mode
address
FFFB F000H
Dummy addresses for auto algorithm