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| 型号： | MB9BF505NBGL |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PBGA112 |
| 封装： | 10 X 10 MM, 1.45 MM HEIGHT, 0.80 MM PITCH, PLASTIC, FBGA-112 |
| 文件页数： | 114/120页 |
| 文件大小： | 1277K |
| 代理商： | MB9BF505NBGL |
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93
8266D-MCU Wireless-06/12
ATmega128RFA1
I/O port control register (DDG0 = 1, PORTG0 = 0, DDF3 = 1, PORTF3 = 0). In this way
the power consumption of external RF switches and other building blocks is reduced
and leakage currents are avoided especially during sleep modes.
9.8.4.2 External RF-Front End Control
The setup time of the external power amplifier (PA) relative to the internal building
blocks should be adjusted when using an external RF front-end including a power
amplifier to optimize the overall power spectral density (PSD) mask.
Figure 9-34. TX Power Ramping Control for RF Front-Ends
0
6
8
10
TRX_STATE
SLPTR
PLL_O N
2
12
14
16
18
Length [ s]
PA buffer
4
PA
PA_BUF_LT
PA_LT
DIG 3
DIG 4
M odulation
1
0 0
0
BU SY_ TX
The start-up sequence of the individual building blocks of the internal transmitter is
shown in the previous figure. The transmission is actually initiated by writing ‘1’ to
SLPTR. The radio transceiver state changes from PLL_ON to BUSY_TX and the PLL
settles to the transmit frequency within 16 s (parameter tTR23 at page 44). The
modulation starts 16 s (parameter tTR10 at page 43) after the SLPTR=1. The PA buffer
and the internal PA are enabled during this time.
The control of an external PA is done via the differential pin pair DIG3 and DIG4.
DIG3 = H / DIG4 = L indicates that the transmission starts and can be used to enable
an external PA. The timing of pins DIG3/DIG4 can be adjusted relative to the start of the
frame and the activation of the internal PA buffer. This is controlled using the register
bits PA_BUF_LT and PA_LT. For details refer to Figure 9-22 on page 79.
9.8.5 RX Frame Time Stamping
To determine the exact timing of an incoming frame e.g. for beaconing networks, the
Symbol Counter should be used. SFD Time Stamping is enabled by setting bit SCTSE
of the Symbol Counter Control Register SCCR0. The actual 32 Bit Symbol Counter
value is captured in the SFD Time Stamp register SCTSR at the time, the SFD has
been received. For details see section "SFD and Beacon Timestamp Generation" on
9.8.6 Configurable Start-Of-Frame Delimiter (SFD)
The SFD is a field indicating the end of the SHR and the start of the packet data. The
length of the SFD is 1 octet (2 symbols). This octet is used for byte synchronization only
and is not included in the Frame Buffer.
The value of the SFD could be changed if it is needed to operate non IEEE 802.15.4
compliant networks. An IEEE 802.15.4 compliant network node does not synchronize to
frames with a different SFD value.
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