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参数资料
| 型号： | MB9BF505NBGL |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PBGA112 |
| 封装： | 10 X 10 MM, 1.45 MM HEIGHT, 0.80 MM PITCH, PLASTIC, FBGA-112 |
| 文件页数： | 115/120页 |
| 文件大小： | 1277K |
| 代理商： | MB9BF505NBGL |
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94
8266D-MCU Wireless-06/12
ATmega128RFA1
The register SFD_VALUE contains the one octet start-of-frame delimiter (SFD) to
synchronize to a received frame. It is not recommended to set the low-order 4 bits to 0
due to the way the SHR is formed.
9.8.7 Dynamic Frame Buffer Protection
The ATmega128RFA1 continues the reception of incoming frames as long as it is in
any receive state. When a frame was successfully received and stored into the Frame
Buffer, the following frame will overwrite the Frame Buffer content again. To relax the
timing requirements for a Frame Buffer read access the Dynamic Frame Buffer
Protection prevents that a new valid frame passes to the Frame Buffer until the buffer
protection bit is cleared (RX_SAFE_MODE = 0).
A received frame is automatically protected against overwriting:
in Basic Operating Mode, if its FCS is valid
in Extended Operating Mode, if an TRX24_RX_END interrupt is generated
The Dynamic Frame Buffer Protection is enabled, if register bit RX_SAFE_MODE
(register TRX_CTRL_2, see "TRX_CTRL_2 – Transceiver Control Register 2" on page
114) is set and the radio transceiver state is RX_ON or RX_AACK_ON.
Note that Dynamic Frame Buffer Protection only prevents write accesses from the air
interface not from the application software. The application software may still modify the
Frame Buffer content.
9.8.8 Security Module (AES)
The security module (AES) is characterized by:
Hardware accelerated encryption and decryption;
Compatible with AES-128 standard (128 bit key and data block size);
ECB (encryption/decryption) mode and CBC (encryption) mode support;
Stand-alone operation, independent of other blocks;
Uses 16MHz crystal clock of the transceiver;
9.8.8.1 Overview
The security module is based on an AES-128 core according to the FIPS197 standard
[5]. and provides two modes, the Electronic Code Book (ECB) and the Cipher Block
Chaining (CBC). The security module works independent of other building blocks of the
radio transceiver. Encryption and decryption can be performed in parallel to a frame
transmission or reception.
During radio transceiver SLEEP the registers of the security engine (AES) are cleared
(see section "SLEEP – Sleep State" on page 37).
The ECB and CBC modules including the AES core are clocked with the 16 MHz Radio
Transceiver Crystal Oscillator.
Controlling the security block is possible over 5 Registers within AVR I/O space:
Table 9-24. Security Module Address Space Overview
Register Name
Description
AES_STATUS
AES status register
AES_CTRL
AES control register
AES_KEY
Access to 16 Byte key buffer
AES_STATE
Access to 16 Byte data buffer
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相关代理商/技术参数 |
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| MB9BF506NABGL-GE1 | 制造商:FUJITSU 功能描述:MCU 32BIT CORTEX-M3 FM3 112BGA 制造商:FUJITSU 功能描述:MCU, 32BIT, CORTEX-M3, FM3, 112BGA, Controller Family/Series:ARM Cortex-M3, Core |
| MB9BF506NAPMC-G-JNE1 | 制造商:FUJITSU 功能描述: 制造商:FUJITSU 功能描述:MCU 32BIT CORTEX-M3 FM3 100LQFP 制造商:FUJITSU 功能描述:MCU, 32BIT, CORTEX-M3, FM3, 100LQFP 制造商:FUJITSU 功能描述:MCU, 32BIT, CORTEX-M3, FM3, 100LQFP, Controller Family/Series:ARM Cortex-M3, Core Size:32bit, No. of I/O's:80, Supply Voltage Min:2.7V, Supply Voltage Max:5.5V, Digital IC Case Style:LQFP, No. of Pins:100, Program Memory Size:512KB, , RoHS Compliant: Yes |
| MB9BF506NBBGL-GE1 | 制造商:FUJITSU 功能描述: |
| MB9BF506NBPMC-G-JNE2 | 制造商:FUJITSU 功能描述: |
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