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参数资料
| 型号： | MBM29F017A-90PFTN |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 2M X 8 FLASH 5V PROM, 90 ns, PDSO48 |
| 封装： | PLASTIC, TSOP1-48 |
| 文件页数： | 11/49页 |
| 文件大小： | 520K |
| 代理商： | MBM29F017A-90PFTN |
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MBM29F017A-70/-90/-12
18
DQ7
Data Polling
The MBM29F017A device features Data Polling as a method to indicate to the host that the embedded algorithms
are in progress or completed. During the Embedded ProgramTM Algorithm, an attempt to read the device will
produce the complement of the data last written to DQ7. Upon completion of the Embedded ProgramTM Algorithm,
an attempt to read the device will produce the true data last written to DQ7. During the Embedded EraseTM
Algorithm, an attempt to read the device will produce a “0” at the DQ7 output. Upon completion of the Embedded
EraseTM Algorithm an attempt to read the device will produce a “1” at the DQ7 output. The flowchart for Data
Polling (DQ7) is shown in “Embedded EraseTM Algorithm” in sFLOW CHART.
Data polling will also flag the entry into Erase Suspend. DQ7 will switch “0” to “1” at the start of the Erase Suspend
mode. Please note that the address of an erasing sector must be applied in order to observe DQ7 in the Erase
Suspend Mode.
During Program in Erase Suspend, Data polling will perform the same as in regular program execution outside
of the suspend mode.
For chip erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence.
For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data Polling
must be performed at sector address within any of the sectors being erased and not a sector that is within a
protected sector group. Otherwise, the status may not be valid.
Just prior to the completion of Embedded Algorithm operation DQ7 may change asynchronously while the output
enable (OE) is asserted low. This means that the device is driving status information on DQ7 at one instant of
time and then that byte's valid data at the next instant of time. Depending on when the system samples the DQ7
output, it may read the status or valid data. Even if the device has completed the Embedded Algorithm operations
and DQ7 has a valid data, the data outputs on DQ6 to DQ0 may be still invalid. The valid data on DQ7 to DQ0 will
be read on the successive read attempts.
The Data Polling feature is only active during the Embedded Programming Algorithm, Embedded Erase Algo-
rithm, Erase Suspend, erase-suspend-program mode, or sector erase time-out. (See “Hardware Sequence
Flags”.)
See “AC Waveforms Chip/Sector Erase Operations” in sTIMING DIAGRAM for the Data Polling timing specifi-
cations and diagrams.
DQ6
Toggle Bit I
The MBM29F017A also features the “Toggle Bit I” as a method to indicate to the host system that the embedded
algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm cycle, successive attempts to read (OE toggling) data from
the device at any address will result in DQ6 toggling between one and zero. Once the Embedded Program or
Erase Algorithm cycle is completed, DQ6 will stop toggling and valid data will be read on
the next successive
attempts. During programming, the Toggle Bit I is valid after the rising edge of the fourth WE pulse in the four
write pulse sequence. For chip erase, the Toggle Bit I is valid after the rising edge of the sixth WE pulse in the
six write pulse sequence. For Sector Erase, the Toggle Bit I is valid after the last rising edge of the sector erase
WE pulse. The Toggle Bit I is active during the sector erase time out.
Either CE or OE toggling will cause the DQ6 to toggle. In addition, an Erase Suspend/Resume command will
cause DQ6 to toggle. See “AC Waveforms for Data Polling During Embedded Algorithm Operations” in sTIMING
DIAGRAM for the Toggle Bit I timing specifications and diagrams.
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