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参数资料
| 型号： | MBM29F017A-90PFTN |
| 厂商： | SPANSION LLC |
| 元件分类： | PROM |
| 英文描述： | 2M X 8 FLASH 5V PROM, 90 ns, PDSO48 |
| 封装： | PLASTIC, TSOP1-48 |
| 文件页数： | 14/49页 |
| 文件大小： | 520K |
| 代理商： | MBM29F017A-90PFTN |
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MBM29F017A-70/-90/-12
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For example, DQ2 and DQ6 can be used together to determine the erase-suspend-read mode. (DQ2 toggles
while DQ6 does not.) See also “Hardware Sequence Flags” and “Temporary Sector Group Unprotection” in
sTIMING DIAGRAM.
Furthermore, DQ2 can also be used to determine which sector is being erased. When the device is in the erase
mode, DQ2 toggles if this bit is read from the erasing sector.
RY/BY
Ready/Busy
The MBM29F017A provides a RY/BY open-drain output pin as a way to indicate to the host system that the
Embedded Algorithms are either in progress or has been completed. If the output is low, the device is busy with
either a program or erase operation. If the output is high, the device is ready to accept any read/write or erase
operation. When the RY/BY pin is low, the device will not accept any additional program or erase commands
with the exception of the Erase Suspend command. If the MBM29F017A is placed in an Erase Suspend mode,
the RY/BY output will be high, by means of connecting with a pull-up resistor to VCC.
During programming, the RY/BY pin is driven low after the rising edge of the fourth WE pulse. During an erase
operation, the RY/BY pin is driven low after the rising edge of the sixth WE pulse. The RY/BY pin will indicate a
busy condition during RESET pulse. Refer to “AC Waveforms for Toggle Bit I During Embedded Algorithm
Operations” in sTIMING DIAGRAM for a detailed timing diagram. The RY/BY pin is pulled high in standby mode.
Since this is an open-drain output, several RY/BY pins can be tied together in parallel with a pull-up resistor to VCC.
RESET
Hardware Reset
The MBM29F017A device may be reset by driving the RESET pin to VIL. The RESET pin must be kept low (VIL)
for at least 500 ns. Any operation in progress will be terminated and the internal state machine will be reset to
the read mode 20 ms after the RESET pin is driven low. If a hardware reset occurs during a program operation,
the data at that particular location will be indeterminate.
When the RESET pin is low and the internal reset is complete, the device goes to standby mode and cannot be
accessed. Also, note that all the data output pins are tri-stated for the duration of the RESET pulse. Once the
RESET pin is taken high, the device requires tRH ns of wake up time until outputs are valid for read access.
The RESET pin may be tied to the system reset input. Therefore, if a system reset occurs during the Embedded
Program or Erase Algorithm, the device will be automatically reset to read mode and this will enable the system’s
microprocessor to read the boot-up firmware from the Flash memory.
Data Protection
The MBM29F017A is designed to offer protection against accidental erasure or programming caused by spurious
system level signals that may exist during power transitions. During power up the device automatically resets
the internal state machine in the Read mode. Also, with its control register architecture, alteration of the memory
contents only occurs after successful completions of specific multi-bus cycle command sequences.
The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up
and power-down transitions or system noise.
Low VCC Write Inhibit
To avoid initiation of a write cycle during VCC power-up and power-down, a write cycle is locked out for VCC less
than VLKO (typically 3.7 V). If VCC < VLKO, the command register is disabled and all internal program/erase circuits
are disabled. Under this condition the device will reset to the read mode. Subsequent writes will be ignored until
the VCC level is greater than VLKO. It is the users responsibility to ensure that the control pins are logically correct
to prevent unintentional writes when VCC is above 3.2 V.
Write Pulse “Glitch” Protection
Noise pulses of less than 5 ns (typical) on OE, CE, or WE will not initiate a write cycle.
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相关代理商/技术参数 |
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|---|---|
| MBM29F017A-90PFTR | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:16M (2M X 8) BIT |
| MBM29F017A-90PNS | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:16M (2M X 8) BIT |
| MBM29F033C | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32M (4M X 8) BIT |
| MBM29F033C-12 | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32M (4M X 8) BIT |
| MBM29F033C-12PTN | 制造商:FUJITSU 制造商全称:Fujitsu Component Limited. 功能描述:32M (4M X 8) BIT |
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