参数资料
型号: MBM29F017A-90PFTN
厂商: SPANSION LLC
元件分类: PROM
英文描述: 2M X 8 FLASH 5V PROM, 90 ns, PDSO48
封装: PLASTIC, TSOP1-48
文件页数: 13/49页
文件大小: 520K
代理商: MBM29F017A-90PFTN
MBM29F017A-70/-90/-12
19
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has exceeded the specified limits (internal pulse count). Under
these conditions DQ5 will produce a “1”. This is a failure condition which indicates that the program or erase
cycle was not successfully completed. Data Polling is the only operating function of the device under this
condition. The CE circuit will partially power down the device under these conditions. The OE and WE pins will
control the output disable functions as described in “MBM29F017A User Bus Operations” in sDEVICE BUS
OPERATION.
The DQ5 failure condition may also appear if a user tries to program a 1 to a location that is previously programmed
to 0. In this case the device locks out and never completes the Embedded ProgramTM Algorithm. Hence, the
system never reads a valid data on DQ7 bit and DQ6 never stops toggling. Once the device has exceeded timing
limits, the DQ5 bit will indicate a “1.” Please note that this is not a device failure condition since the device was
incorrectly used. If this occurs, reset the device.
DQ3
Sector Erase Timer
After the completion of the initial sector erase command sequence the sector erase time-out will begin. DQ3 will
remain low until the time-out is complete. Data Polling and Toggle Bit I are valid after the initial sector erase
command sequence.
If Data Polling or the Toggle Bit I indicates the device has been written with a valid erase command, DQ3 may
be used to determine if the sector erase timer window is still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent commands (other than Erase Suspend) to the device will
be ignored until the erase operation is completed as indicated by Data Polling or Toggle Bit I. If DQ3 is low (“0”),
the device will accept additional sector erase commands. To insure the command has been accepted, the system
software should check the status of DQ3 prior to and following each subsequent sector erase command. If DQ3
were high on the second status check, the command may not have been accepted.
Refer to “Hardware Sequence Flags”
DQ2
Toggle Bit II
This toggle bit, along with DQ6, can be used to determine whether the device is in the Embedded EraseTM
Algorithm or in Erase Suspend.
Successive reads from the erasing sector will cause DQ2 to toggle during the Embedded EraseTM Algorithm. If
the device is in the erase-suspended-read mode, successive reads from the erase-suspended sector will cause
DQ2 to toggle. When the device is in the erase-suspended-program mode, successive reads from the byte
address of the non-erase suspended sector will indicate a logic “1” at the DQ2 bit.
DQ6 is different from DQ2 in that DQ6 toggles only when the standard program or Erase, or Erase Suspend
Program operation is in progress. The behavior of these two status bits, along with that of DQ7, is summarized
as follows:
*1 : These status flags apply when outputs are read from a sector that has been erase-suspended.
*2 : These status flags apply when outputs are read from the byte address of the non-erase suspended sector.
Mode
DQ7
DQ6
DQ2
Program
DQ7
Toggle
1
Erase
0
Toggle
Erase Suspend Read *1
(Erase-Suspended Sector)
11
Toggle
Erase Suspend Program
DQ7 *2
Toggle
1 *2
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