参数资料
| 型号： | MC14LC5540DW |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 27/28页 |
| 文件大小： | 0K |
| 描述： | IC CODEC ADPCM 28-SOIC W |
| 标准包装： | 26 |
| 类型： | ADPCM 编解码器/滤波器 |
| 数据接口： | PCM 音频接口 |
| 分辨率（位）： | 13 b |
| ADC / DAC 数量： | 1 / 1 |
| 三角积分调变： | 无 |
| 电压 - 电源，数字： | 4.5V ~ 5.5V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 管件 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页当前第27页第28页
MC145484
MOTOROLA
8
Long Frame Sync
Long Frame Sync is the industry name for one type of
clocking format that controls the transfer of the PCM data
words. (Refer to Figure 2a.) The ‘‘Frame Sync’’ or ‘‘Enable’’ is
used for two specific synchronizing functions. The first is to
synchronize the PCM data word transfer, and the second is
to control the internal analog–to–digital and digital–to–analog
conversions. The term ‘‘Sync’’ refers to the function of syn-
chronizing the PCM data word onto or off of the multiplexed
serial PCM data bus, which is also known as a PCM high-
way. The term ‘‘Long’’ comes from the duration of the frame
sync measured in PCM data clock cycles. Long Frame Sync
timing occurs when the frame sync is used directly as the
PCM data output driver enable. This results in the PCM out-
put going low impedance with the rising edge of the transmit
frame sync, and remaining low impedance for the duration of
the transmit frame sync.
The implementation of Long Frame Sync has maintained
compatibility and been optimized for external clocking sim-
plicity. This optimization includes the PCM data output going
low impedance with the logical AND of the transmit frame
sync (FST) with the transmit data bit clock (BCLKT). The op-
timization also includes the PCM data output (DT) remaining
low impedance until the middle of the LSB (seven and a half
PCM data clock cycles) or until the FST pin is taken low,
whichever occurs last. This requires the frame sync to be
approximately rising edge aligned with the initiation of the
PCM data word transfer, but the frame sync does not have a
precise timing requirement for the end of the PCM data word
transfer. The device recognizes Long Frame Sync clocking
when the frame sync is held high for two consecutive falling
edges of the transmit data clock. The transmit logic decides
on each frame sync whether it should interpret the next
frame sync pulse as a Long or a Short Frame Sync. This de-
cision is used for receive circuitry also. The device is de-
signed to prevent PCM bus contention by not allowing the
PCM data output to go low impedance for at least two frame
sync cycles after power is applied or when coming out of the
powered down mode.
The receive side of the device is designed to accept the
same frame sync and data clock as the transmit side and to
be able to latch its own transmit PCM data word. Thus the
PCM digital switch needs to be able to generate only one
type of frame sync for use by both transmit and receive sec-
tions of the device.
The logical AND of the receive frame sync with the receive
data clock tells the device to start latching the 8–bit serial
word into the receive data input on the falling edges of the
receive data clock. The internal receive logic counts the re-
ceive data clock cycles and transfers the PCM data word to
the digital–to–analog converter sequencer on the ninth data
clock rising edge.
This device is compatible with four digital interface modes.
To ensure that this device does not reprogram itself for a dif-
ferent timing mode, the BCLKR pin must change logic state
no less than every 125
s. The minimum PCM data bit clock
frequency of 64 kHz satisfies this requirement.
Short Frame Sync
Short Frame Sync is the industry name for the type of
clocking format that controls the transfer of the PCM data
words (refer to Figure 2b). The ‘‘Frame Sync’’ or ‘‘Enable’’ is
used for two specific synchronizing functions. The first is to
synchronize the PCM data word transfer, and the second is
to control the internal analog–to–digital and digital–to–analog
conversions. The term ‘‘Sync’’ refers to the function of syn-
chronizing the PCM data word onto or off of the multiplexed
serial PCM data bus, which is also known as a PCM high-
way. The term ‘‘Short’’ comes from the duration of the frame
sync measured in PCM data clock cycles. Short Frame Sync
timing occurs when the frame sync is used as a ‘‘pre–syn-
chronization’’ pulse that is used to tell the internal logic to
clock out the PCM data word under complete control of the
data clock. The Short Frame Sync is held high for one falling
data clock edge. The device outputs the PCM data word be-
ginning with the following rising edge of the data clock. This
results in the PCM output going low impedance with the ris-
ing edge of the transmit data clock, and remaining low im-
pedance until the middle of the LSB (seven and a half PCM
data clock cycles).
The device recognizes Short Frame Sync clocking when
the frame sync is held high for one and only one falling edge
of the transmit data clock. The transmit logic decides on each
frame sync whether it should interpret the next frame sync
pulse as a Long or a Short Frame Sync. This decision is used
for receive circuitry also. The device is designed to prevent
PCM bus contention by not allowing the PCM data output to
go low impedance for at least two frame sync cycles after
power is applied or when coming out of the powered down
mode.
The receive side of the device is designed to accept the
same frame sync and data clock as the transmit side and to
be able to latch its own transmit PCM data word. Thus the
PCM digital switch needs to be able to generate only one
type of frame sync for use by both transmit and receive sec-
tions of the device.
The falling edge of the receive data clock latching a high
logic level at the receive frame sync input tells the device to
start latching the 8–bit serial word into the receive data input
on the following eight falling edges of the receive data clock.
The internal receive logic counts the receive data clock
cycles and transfers the PCM data word to the digital–to–
analog converter sequencer on the rising data clock edge af-
ter the LSB has been latched into the device.
This device is compatible with four digital interface modes.
To ensure that this device does not reprogram itself for a dif-
ferent timing mode, the BCLKR pin must change logic state
no less than every 125
s. The minimum PCM data bit clock
frequency of 64 kHz satisfies this requirement.
Interchip Digital Link (IDL)
The Interchip Digital Link (IDL) Interface is one of two
standard synchronous 2B+D ISDN timing interface modes
with which this device is compatible. In the IDL mode, the de-
vice can communicate in either of the two 64 kbps B chan-
nels (refer to Figure 2c for sample timing). The IDL mode is
selected when the BCLKR pin is held high for two or more
FST (IDL SYNC) rising edges. The digital pins that control
the transmit and receive PCM word transfers are repro-
grammed to accommodate this mode. The pins affected are
FST, FSR, BCLKT, DT, and DR. The IDL Interface consists of
four pins: IDL SYNC (FST), IDL CLK (BCLKT), IDL TX (DT),
and IDL RX (DR). The IDL interface mode provides access to
both the transmit and receive PCM data words with common
control clocks of IDL Sync and IDL Clock. In this mode, the
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
AR
CH
IVE
D B
Y F
RE
ES
CA
LE
SE
MI
CO
ND
UC
TO
R,
INC
.
相关PDF资料 |
PDF描述 |
|---|---|
| MC33199DR2 | IC DRVR SER INK ISO9141 14-SOIC |
| MC33215BE | IC SPEAKERPHONE CIRCUIT 42-SDIP |
| MC33990DR2 | IC TRANSCEIVER J-1850 BUS 8-SOIC |
| MC34017A-3P | IC PHONE TONE RINGER 500HZ 8-DIP |
| MC34018DWR2 | IC SPEAKERPHONE VOICE SW 28-SOIC |
相关代理商/技术参数 |
参数描述 |
|---|---|
| MC14N-S-10230AC | 制造商:IMO 功能描述:Contactor 3 Pole Open 5.5kW 14A AC3, 1 Normally Open Auxiliary, 230V AC Coil Ove |
| MC14-S-10110 | 制造商:IMO Precision Controls Ltd 功能描述:CONTACTOR 5.5KW 110VAC 制造商:IMO Precision Controls Ltd 功能描述:CONTACTOR 1NO 110VAC 14A D 制造商:IMO PRECISION CONTROLS 功能描述:CONTACTOR, 5.5KW, 110VAC 制造商:IMO Precision Controls Ltd 功能描述:CONTACTOR, 1NO, 110VAC, 14A, DIN RAIL; Operating Voltage:690VAC; Switching Power AC1:4kW; Switching Power AC3:7.5kW; Switching Current AC1:25A; Switching Current AC3:14A; Load Current Inductive:14A; Load Current Resistive:25A ;RoHS Compliant: Yes |
| MC14-S-10110 | 制造商:IMO Precision Controls Ltd 功能描述:CONTACTOR 4KW/10A 110VAC |
| MC14-S-10230 | 制造商:IMO Precision Controls Ltd 功能描述:CONTACTOR 5.5KW 230VAC 制造商:IMO Precision Controls Ltd 功能描述:CONTACTOR 1NO 230VAC 14A D 制造商:IMO PRECISION CONTROLS 功能描述:CONTACTOR, 5.5KW, 230VAC 制造商:IMO Precision Controls Ltd 功能描述:CONTACTOR, 1NO, 230VAC, 14A, DIN RAIL; Operating Voltage:690VAC; Switching Power AC1:4kW; Switching Power AC3:7.5kW; Switching Current AC1:25A; Switching Current AC3:14A; Load Current Inductive:14A; Load Current Resistive:25A ;RoHS Compliant: Yes |
| MC14-S-10230 | 制造商:IMO Precision Controls Ltd 功能描述:CONTACTOR 4KW/10A 230VAC |
发布紧急采购，3分钟左右您将得到回复。