参数资料
| 型号： | MC14LC5540DW |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 4/28页 |
| 文件大小： | 0K |
| 描述： | IC CODEC ADPCM 28-SOIC W |
| 标准包装： | 26 |
| 类型： | ADPCM 编解码器/滤波器 |
| 数据接口： | PCM 音频接口 |
| 分辨率（位）： | 13 b |
| ADC / DAC 数量： | 1 / 1 |
| 三角积分调变： | 无 |
| 电压 - 电源，数字： | 4.5V ~ 5.5V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 管件 |
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MC145484
MOTOROLA
12
ANALOG ELECTRICAL CHARACTERISTICS (VDD = + 5 V ± 10%, VSS = 0 V, TA = – 40 to + 85°C)
Characteristics
Min
Typ
Max
Unit
Input Current
TI+, TI–
—
± 0.1
± 1.0
A
Input Resistance to VAG (VAG – 0.5 V ≤ Vin ≤ VAG + 0.5 V)
TI+, TI–
10
—
—
M
Input Capacitance
TI+, TI–
—
10
pF
Input Offset Voltage of TG Op Amp
TI+, TI–
—
± 5
mV
Input Common Mode Voltage Range
TI+, TI–
1.2
VDD – 2.0
V
Input Common Mode Rejection Ratio
TI+, TI–
—
60
—
dB
Gain Bandwidth Product (10 kHz) of TG Op Amp (RL ≥ 10 k)
—
3000
—
kHz
DC Open Loop Gain of TG Op Amp (RL ≥ 10 k)
—
95
—
dB
Equivalent Input Noise (C–Message) Between TI+ and TI– at TG
—
–30
—
dBrnC
Output Load Capacitance for TG Op Amp
0
—
100
pF
Output Voltage Range for TG
(RL = 10 k to VAG)
(RL = 2 k to VAG)
0.5
1.0
—
VDD – 0.5
VDD – 1.0
V
Output Current (0.5 V
≤ Vout ≤ VDD – 0.5 V)
TG, RO–
± 1.0
—
mA
Output Load Resistance to VAG
TG, RO–
2
—
k
Output Impedance (0 to 3.4 kHz)
RO–
—
1
—
Output Load Capacitance
RO–
0
—
500
pF
DC Output Offset Voltage of or RO– Referenced to VAG
—
± 25
mV
VAG Output Voltage Referenced to VSS (No Load)
VDD/2 – 0.1
VDD/2
VDD/2 + 0.1
V
VAG Output Current with ± 25 mV Change in Output Voltage
± 2.0
± 10
—
mA
Power Supply Rejection Ratio
Transmit
(0 to 100 kHz @100 mVrms Applied to VDD,
Receive
C–Message Weighting, All Analog Signals
Referenced to VAG Pin)
50
80
75
—
dBC
Power Drivers PI, PO+, PO–
Input Current (VAG – 0.5 V ≤ PI ≤ VAG + 0.5 V)
PI
—
± 0.05
± 1.0
A
Input Resistance (VAG – 0.5 V ≤ PI ≤ VAG + 0.5 V)
PI
10
—
M
Input Offset Voltage
PI
—
± 20
mV
Output Offset Voltage of PO+ Relative to PO– (Inverted Unity Gain for PO–)
—
± 50
mV
Output Current (VSS + 0.7 V ≤ PO+ or PO– ≤ VDD – 0.7 V)
± 10
—
mA
PO+ or PO– Output Resistance (Inverted Unity Gain for PO–)
—
1
—
Gain Bandwidth Product (10 kHz, Open Loop for PO–)
—
1000
—
kHz
Load Capacitance (PO+ or PO– to VAG, or PO+ to PO–)
0
—
1000
pF
Gain of PO+ Relative to PO– (RL = 300 , + 3 dBm0, 1 kHz)
– 0.2
0
+ 0.2
dB
Total Signal to Distortion at PO+ and PO– with a Differential Load of:
300
100 nF in series with
≥ 20
≥ 100
45
—
60
40
—
dBC
Power Supply Rejection Ratio
0 to 4 kHz
(0 to 25 kHz @ 100 mVrms Applied to VDD.
4 to 25 kHz
PO– Connected to PI. Differential or Measured
Referenced to VAG Pin.)
40
—
55
40
—
dB
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